Lampros Dermentzoglou

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). The proposed test-circuit is capable of detecting hard (catastrophic) and soft (parametric) faults, injected in the VCO. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit. The overall silicon area requirement of the proposed DFT scheme is negligible.

An extra low noise 1.8 GHz voltage controlled oscillator in 0.35 SiGe BiCMOS technology

A fully integrated 1.8 GHz low-phase-noise LC-tank voltage controlled oscillator (VCO) has been designed in SiGe BiCMOS technology. The noise performance is partially due to the high Q SiGe thick Metal5 octagonal inductors and n/sup +//n-well on p-substrate varactors used in the LC tank and also due to the large MOSFETs used in the cross-coupled pair in order to compensate the inductor losses. The phase noise achieved is -120.7 dBc/Hz at an offset frequency of 200 kHz, considering a current consumption of 15 mA, with 3.3 V power supply. The tunability of the structure covers 216 MHz, from 1.612 GHz up to 1.828 GHz.

An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers

This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Amplifiers (LNAs). The ETC operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amplitude (gain reduction). The ETC along with a single ended LNA have been designed in a 0.35 mum CMOS technology to evaluate the efficiency of the proposed approach and experimental results are presented.

A test technique and a BIST circuit to detect catastrophic faults in RF Mixers

A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixers is presented in this paper. During test application the Mixer is set to operate in homodyne mode and the DC levels generated at its outputs are used as test observables. These test observables are converted to digital signatures, by a simple embedded circuit, and are used to discriminate fault free from faulty Mixers. The proposed technique has been applied to a typical differential RF Mixer designed in a 0.18μm CMOS technology. Simulation results validated its efficiency to provide a high coverage of catastrophic faults which exceeds 90%.

A built-in self-test scheme for differential ring oscillators

In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults can be either short or bridging faults between circuit nodes or open faults at the circuit branches. The test result is provided by a digital fail/pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique regarding its fault coverage.

ANALOG-TO-DIGITAL INTERFACE FOR HETERODYNE RECEIVERS

The analysis of the Intermediate Frequency (IF) section of a heterodyne receiver employing IF sampling, based on its Carrier-to-Interference ratio (C/I), yields various options on filtering, amplification, conversion to digital and interfacing to base-band. These options are considered using Bit Error Rate (BER) simulations, leading to an optimized design for the IF section and the interface to base-band of the heterodyne receiver.

A static differential double edge-triggered flip–flop based on clock racing

Abstract In this paper, a double edge-triggered (DET) flip–flop is proposed, suitable for high-performance and low-power applications. The presented flip–flop has differential structure and provides static operation. The double edge triggering operation is achieved, by generating a narrow pulse immediately after each clocking edge, which is used to set the flip–flop in the transparent phase. The narrow pulse generation technique is based on a clock racing methodology. Compared to existing DET flip–flops, the proposed DET flip–flop results in significant delay and power gains, but keeps the total transistor count low. By applying the narrow pulse to more than one similar adjacent DET flip–flops, we can further reduce the power and the transistor count.

A novel scheme for testing radio frequency voltage controlled oscillators

In this paper, a novel scheme for testing LC-tank CMOS Voltage Controlled Oscillators (VCOs) is presented. The proposed test circuit is capable of detecting soft and hard faults in a percentage that can guarantee safe overall fault coverage. It has been realized that the proposed technique is capable of detecting open and short circuits as well as process variations outside the specified limits in the passive components of the VCO in a percentage that exceeds 93%. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit, which additionally presents negligible silicon area requirements in the design process.

A design for testability technique for mixed-signal differential circuits*

In this paper a new DFT scheme is proposed suitable for testing mixed signal differential circuits. The proposed testing-scheme is capable of detecting single catastrophic faults injected into the circuit under test. These faults can be either shorts and opens or bridgings between non contiguous nodes of the circuit. The test result is provided by a digital fail/pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique in terms of fault coverage and cost.

A 0.35 /spl mu/m SiGe BiCMOS front end for GSM low IF cellular receiver applications

This work presents the design and simulation of a cellular receiver front end for GSM applications implemented in 0.35 SiGe BiCMOS technology. The low noise amplifier is designed using bipolar transistors, and achieves a voltage gain of 17 dB at 950 MHz, while its noise figure is suppressed to 1.9 dB in the same frequency region. The resulting 1 dB compression point is -12 dBm and the IIP3 is -3 dBm. The mixer is a double balanced Gilbert cell performing an IIP3 of 14 dBm, while the single sideband noise figure is around 12 dB. The whole structure is oriented to low IF receiver applications while the overall power consumption is 31 mW provided from a 3.3 V power supply.