Angela Krstic

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

Fast statistical timing analysis by probabilistic event propagation

We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for cell-based designs with all cell delays modeled as random variables. Our algorithm propagates probabilistic timing events through the circuit and obtains final probabilistic events (distributions) at all nodes. The new algorithm is deterministic and flexible in controlling run time and accuracy. However, the algorithm has exponential time complexity for circuits with reconvergent fanouts. In order to solve this problem, we further propose a fast approximate algorithm. Experiments show that this approximate algorithm speeds up the statistical timing analysis by at least an order of magnitude and produces results with small errors when compared with Monte Carlo methods.

Embedded software-based self-test for programmable core-based designs

The programmable cores on SoCs can perform on-chip test generation, measurement, response analysis, and even diagnosis. This software-based approach to self-testing enables at-speed testing and incurs low DFT overhead. We give an overview of the existing embedded software-based self-testing and self-diagnosis methods for core-based SoC designs, and we discuss the challenges to further developing this new testing paradigm.

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Noise effects such as power supply and crosstalk noise can significantly impact the performance of deep submicrometer designs. Existing delay testing and timing analysis techniques cannot capture the effects of noise on the signal/cell delays. Therefore, these techniques cannot capture the worst case timing scenarios and the predicted circuit performance might not reflect the worst case circuit delay. More accurate and efficient timing analysis and delay testing strategies need to be developed to predict and guarantee the performance of deep submicrometer designs. In this paper, we propose a new pattern generation technique for delay testing and dynamic timing analysis that can take into account the impact of the power supply noise on the signal propagation delays. In addition to sensitizing the selected paths, the new patterns also cause high power supply noise on the nodes in these paths. Thus, they also cause longer propagation delays for the nodes along the paths. Our experimental results on benchmark circuits show that the new patterns produce significantly longer delays on the selected paths compared to the patterns derived using existing pattern generation methods.

New challenges in delay testing of nanometer, multigigahertz designs

Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. We examine the challenges in meeting the quality requirements of gigascale integration, and explore functional testing as well as statistical models and methods that could alleviate some of those problems.

Delay testing considering crosstalk-induced effects

Increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performance degradation and must be addressed both in the design for deep submicron and testing for deep submicron phases. Existing delay testing techniques cannot capture the effects of noise on the cell/interconnect delays. In this paper, we address the problem of delay testing considering crosstalk-induced delay effects. We propose solutions for target fault selection and pattern generation. The key elements of our strategy are performance sensitivity analysis with respect to crosstalk noise and a genetic algorithm (GA) based vector generation technique. The role of performance sensitivity analysis is to consider the effects of crosstalk noise during the target fault selection process. Next, for each selected fault consisting of a path and a set of crosstalk noise sources interacting with the path, we apply our iterative GA-based pattern generation process. Our goal is to derive a test that produces a large crosstalk-induced delay effect on the given path. Our technique allows consideration of any number of coupling sources along the target path. Due to its flexibility, efficiency and scalability, the technique can be applied to large circuits.

Vector generation for maximum instantaneous current through supply lines for CMOS circuits

We present two new algorithms for generating a smallset of patterns for estimating the maximum instantaneouscurrent through the power supply lines for CMOScircuits.The first algorithm is based on timed ATPG,while the second is a probability-based approach.Bothalgorithms can handle circuits with arbitrary but knowndelays and they produce a set of 2-vector tests.Experimentalresults demonstrating that the outcome of applyingour algorithms is a small set of patterns producinga current that is a tight lower bound on the maximuminstantaneous current are included.

Post-layout logic restructuring for performance optimization

We propose a new methodology based on incrementallogic restructuring for post-layout performance improvement.The new post-layout logic restructuring techniqueallows to use accurate interconnection delays for performanceoptimization, while the incremental nature of thetechnique guarantees convergence between logic synthesisand layout. The technique can be further integrated withother post-layout optimization techniques such as gate sizingand buffer insertion. Experimental results show that thistechnique combined with post-layout buffer insertion canachieve an additional 15% improvement in performancecompared to designs produced by timing-driven logic optimizationfollowed by pre-layout buffer insertion followedby timing-driven physical design.

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In this paper, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure. We apply the proposed path selection technique for selection of a set of paths for dynamic timing analysis considering power supply noise effects. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored. Thus, they indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.

Generation of high quality tests for robustly untestable path delay faults

In many designs a large portion of path delay faults is not robustly testable. In this paper, we investigate testing strategies for robustly untestable faults. We show that the quality of nonrobust tests may be very poor in detecting small defects caused by manufacturing process variation. We demonstrate that better quality nonrobust tests can be obtained by including timing information into the process of test generation. A good nonrobust test can tolerate larger timing variations on the off-inputs. We also show that not all nonrobustly untestable path delay faults may be ignored in high quality delay testing. Functional sensitizable paths are nonrobustly untestable but, under some faulty conditions, may degrade the performance of the circuit. However, up till now, there was no strategy for generating tests for such faults. In this paper, we present algorithms for generating high quality nonrobust and functional sensitizable tests. We also devise an algorithm for generating tests for validatable nonrobust faults which have a high quality in detecting defects but are hard to be generated automatically. Our experimental results show that the quality of delay testing increases if validatable and high quality nonrobust tests, as well as tests for functional sensitizable path delay faults are included.