T. M. Mak

Defect and error tolerance in the presence of massive numbers of defects

As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. We introduce a new approach for error tolerance resulting in chips containing only error acceptable for such applications.

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

Built-In Soft Error Resilience for Robust System Design

Built-in soft error resilience (BISER) is an architecture-aware circuit design technique for correcting soft errors in latches, flip-flops and combinational logic. BISER enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 6-10% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several traditional error-detection techniques introduce 40-100% power, performance and area penalties, and require significant efforts for designing and validating corresponding recovery mechanisms. In addition, BISER enables system design with configurable soft error protection features. Such features are extremely important for future designs targeting applications with a wide range of power, performance and reliability constraints. Design trade-offs associated with BISER and other existing soft error protection techniques are also analyzed.

Do we need anything more than single bit error correction (ECC)

For a long time, single bit error correction (with double bit error detection) has been the mainstay ECC technology for covering soft errors in the cache. From the soft error rate that has been observed (at least terrestrially), people have been content with what single bit correction can offer. For the rare occasion that a double error occurs, ECC will also be able to alert the system and result in a graceful shutdown or otherwise. However, things are changing. As technology scaling continues, we are approaching the point where we will have a billion transistors on a single piece of silicon, with a big part of this budget as memory elements. In a system, the number of memory bits is also on the rise. The scaled technology also brings with it many variations and sensitivities that can cause memory cells to function improperly, or may not function well at certain environmental conditions. Increasingly, ECC is no longer serving as just radiation induced soft error correction, but may be able to affect other forms of fault corrections as well. Will ECC be able to serve this multi-faceted role? Do we need more than single bit error correction? Can we afford the cost of multiple bit error correction? Should we need it? This paper will attempt to answer some of these questions and raise issues with the status quo.

Logic soft errors: a major barrier to robust platform design

Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques

Implications of clock distribution faults and issues with screening them during manufacturing testing

Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself.

Elimination of traditional functional testing of interface timings at intel

This work summarizes the design for test (DFT) circuitry and test methods that enabled Intel to shift away from traditional functional testing of I/Os. This shift was one of the key enablers for automatic test equipment (ATE) re-use and the move to lower capability (& cost) structural test platforms. Specific examples include circuit implementations from the Pentium/sup /spl reg// 4 processor, high volume manufacturing (HVM) data, and evolutionary changes to address key learnings. We close with indications of how this can be extended to cover the next generation high speed serial like interfaces.

Design for Resilience to Soft Errors and Variations

This paper presents adaptive variation-and-error-resilient agent (AVERA), an approach to address the challenge of designing reliable systems in the presence of soft errors and variations. AVERA extends our previous built-in soft error resilience (BISER) approach by adding additional capabilities to support process variation diagnosis, degradation detection, and system adaptation, besides soft error correction. We also discuss open challenges for building variation-and-error-resilient systems.

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs.

An industrial case study for X-canceling MISR

An X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output streams containing unknown (X) values was described in [Touba 07]. Unlike conventional approaches, it does not use X-masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the Xs. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together to cancel out all X values and yield deterministic values. This new X-canceling approach was applied to some industrial designs under the constraints imposed by an industrial test environment. Practical issues for implementing X-canceling are discussed, and a new architecture for implementing X-canceling based on using a shadow register with multiple selective XORs is presented. Experimental results are shown for industrial designs comparing the performance of X-canceling with X-compact.