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Dive into the research topics where Manoj Dusanapudi is active.

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Featured researches published by Manoj Dusanapudi.


design automation conference | 2014

Post-Silicon Validation of the IBM POWER8 Processor

Amir Nahir; Manoj Dusanapudi; Shakti Kapoor; Kevin Franklin Reick; Wolfgang Roesner; Klaus-Dieter Schubert; Keith Sharp; Greg Wetli

The post-silicon validation phase in a processors design life cycle is geared towards finding all remaining bugs in the system. It is, in fact, our last opportunity to find functional and electrical bugs in the design before shipping it to customers. In this paper, we provide a high-level overview of the methodology and technologies put into use as part of the POWER8 post-silicon functional validation phase. We describe the results and list the primary factors that contributed to this highly successful bring-up.


Ibm Journal of Research and Development | 2015

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Manoj Dusanapudi; S. Fields; Michael Stephen Floyd; Guy Lynn Guthrie; Ronald Nick Kalla; Shakti Kapoor; Larry Scott Leitner; C. F. Marino; Joseph McGill; Amir Nahir; Kevin Franklin Reick; Hugh Shen; Kenneth L. Wright

Debugging post-silicon fails continues to be a difficult problem that is becoming even more challenging as chips integrate more functionality and implement increasingly complicated functions. Additionally, the complexity of hardware systems, coupled with the difficulty in observing the state of the system that led to the failure, make the debugging effort a unique challenge. In this paper, we review the techniques and mechanisms used to facilitate effective debugging in the POWER8™ processor post-silicon validation phase. We further describe several functional bugs and describe the debugging process that drove the identification of their root cause.


Archive | 2007

System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

Vinod Bussa; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil; Bhavani Shringari Nanjundiah


Archive | 2007

System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation

Sampan Arora; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Chakrapani Rayadurgam


Archive | 2007

System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Sandip Bag; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Bhavani Shringari Nanjundiah


Archive | 2007

System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil


Archive | 2007

System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation

Sampan Arora; Sandip Bag; Vinod Bussa; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Batchu Naga Venkata Satyanarayana; Shiraz Mohammad Zaman


Archive | 2007

System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Chakrapani Rayadurgam; Batchu Naga Venkata Satyanarayana


Archive | 2007

System and method for generating fast instruction and data interrupts for processor design verification and validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil


Archive | 2007

System and Method for Testing a Large Memory Area During Processor Design Verification and Validation

Divya S. Anvekar; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor

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