Anil Celebi

A Low-Complexity Approach for the Color Display of Hyperspectral Remote-Sensing Images Using One-Bit-Transform-Based Band Selection

This paper presents a new approach for the color display of hyperspectral images. It is proposed to use the one-bit transform (1BT) of hyperspectral image bands to select three suitable bands for red, green, and blue (RGB) display. The proposed approach has low complexity and is very suitable for hardware implementation. A dedicated hardware architecture that computes the transitions in the 1BT of hyperspectral image bands to determine bands that contain more information and the corresponding field-programmable gate array implementation of the proposed architecture are presented. In the proposed approach, less-structured bands are initially eliminated using the total number of transitions in the 1BT of hyperspectral image bands. Then, three suitable bands are selected from within this remaining set of well-structured bands for RGB color display. The proposed approach provides a new method for facilitating the color display of hyperspectral images, which has very low complexity.

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

An all binary sub-pixel motion estimation approach and its hardware architecture

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices.

Truncated gray-coded bit-plane matching based motion estimation and its hardware architecture

In this paper, an efficient low bit-depth representation based motion estimation approach which is particularly suitable for low-power mobile devices is proposed. Motion estimation is carried out using bit truncated gray-coded image pixels in the proposed approach. The hardware architecture of the proposed motion estimation method is also designed to show the effectiveness of the proposed approach. It is shown that the proposed approach provides improved motion estimation accuracy compared to the other bit-truncation based approaches. The proposed hardware architecture has low hardware complexity and consumes very low power compared to the 8-bits/pixel based hardware architectures thus, it can be easily integrated to the state of the art video encoders.

Selective gray-coded bit-plane based low-complexity motion estimation and its hardware architecture

Today, many consumer electronics devices have video capturing capability which is one of the most time, power and memory consuming application. Motion estimation (ME) is the key part of the video coding process in terms of computational load. Thus, it is important to implement this process in a resource efficient way without degrading the encoding quality and real-time operation performance. Low bitdepth representation based ME methods draw a lot of attention in consumer electronics area mainly thanks to its highly efficient hardware and software implementations. However, these low bit-depth representation based methods generally assume that the low bit-depth images are already available. Furthermore, these methods simply neglect the binarization cost which is not a proper approach when whole encoding architecture is of concern. This paper presents a novel selective Gray-coding based ME method and its hardware architecture with an embedded system integration by making use of one of the most common interconnect architecture in consumer electronics devices. Experimental results show that it is possible to reduce computational load of binarization stage significantly while improving the ME accuracy by the proposed approach compared to methods at the same category.

FPGA implementation of cubic spline interpolation method for empirical mode decomposition

In this work, cubic spline interpolation method is implemented on a field programmable gate array (FPGA) to be used for real time empirical mode decomposition. Different from the software implementation of the method, in the hardware implementation, a hardware architecture is designed with performance and resource usage under consideration. According to the experimental results, the hardware architecture performed the computation approximately 900 times faster compared to the software implementation. The designed hardware architecture is successfully integrated with empirical mode decomposition (EMD) method which generally is utilized as a building block of classification methods proposed in the literature.

A 10-Bit 500Ms/s Two-Step Flash ADC

In this article, a novel 10-bit two-step flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented. The simulation results include 1.5V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s. The process parameter and temperature variation analysis of the converter is especially included. The DC simulation results show linearity measures of less than 0.1 LSB DNL and INL for each 5-bit flash core. The active chip area is 1.4mm2 in 0.5mum CMOS technology

On the FPGA implementation of empirical mode decomposition algorithm using FPGA

In this paper a single chip hardware architecture for empirical mode decomposition is proposed and implemented on a consumer grade FPGA device. Implementing EMD on a single chip dramatically decreases hardware costs and increases real time processing performance. Proposed hardware architecture has utilized %17 of the LUT resources of a consumer grade FPGA. Even though the proposed architecture operates on single dimensional signals such as EEG, sound etc., it can also be considered for decomposing multidimensional signals such as image, video, hyper spectral images.

An uncooled infrared camera with embedded real-time target tracking capability

In this paper an uncooled infrared camera with embedded target detection and tracking capability is presented. The camera is built upon four main electronic cards. Sensor card is designed to read and digitize the analog output signal generated by the infrared (IR) imaging sensor. FPGA card carries out the control process of the data transfer between sensor card and other peripherals. Target detection/tracking task is on the row image data provided by the FPGA card is carried out on the DSP card. Frame thresholding and differencing methods are used for target detection. Kalman filter is utilized for target tracking. According to the experimental results, camera is capable of performing target detection and tracking tasks in real time.

Integer 1-bit transform method and its hardware architecture for low-complexity block-based motion estimation

The need for coding efficiency is being increased with applications in which high resolution video processing is being performed. Power consumption and memory are important constraints for devices capable of recording and transmitting video, such as ultra-high definition televisions (UHD TVs), cameras, smartphones. In video encoders, motion estimation is the process which utilizes the most complex tasks and consumes most of the power. Therefore, low complexity motion estimation methods have been developed which can provide efficient hardware architectures. In this work, a novel integer 1-bit transform method is proposed. Additionally, proposed method and multiplication-free one bit transform method are compared by taking hardware cost which originates from binarization process into account and experimental results are presented.