Oguzhan Urhan

Constrained One-Bit Transform for Low Complexity Block Motion Estimation

One-bit transform (1BT)- and two-bit transform (2BT)-based block motion estimation (ME) schemes have been proposed in the literature to reduce the computational complexity of the ME process by enabling simple Boolean ex-or matching of lower bit depth representations of image frames. Recently a multiplication-free 1BT (MF-1BT) has been proposed to facilitate 1BT to be carried out with integer arithmetic using addition and shifts only. Thresholding schemes are typically used in order to construct the lower bit depth representations utilized in 1BT and 2BT. In our experience we have observed that one problem with such schemes is that pixel values that lie on directly opposite sides of the threshold are categorized into separate classes and are, therefore, counted as a nonmatch in the search process even if they are close in value. A constrained 1BT (C-1BT) that restricts pixels with values adjacent to the transform threshold during 1BT matching, counting them as a match regardless of their 1BT value, is proposed in this paper. It is shown that the proposed C-1BT approach improves the ME accuracy of 1BT-based ME and even outperforms 2BT-based ME at macroblock level

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

Scratch detection via temporal coherency analysis and removal using edge priority based interpolation

This paper presents an automatic scratch detection and removal approach for archive film sequences. The proposed detector mainly exploits temporal coherency of candidate scratch positions, which are obtained using an automatic scratch detection method proposed in the literature. In the restoration stage, both spatial and temporal information are employed. The proposed edge priority based scratch removal algorithm successfully removes scratch effects from archive film sequences

Constrained one-bit transform-based motion estimation using predictive hexagonal pattern

We combine predictive hexagonal pattern and partial distortion searches with the recently proposed constrained one-bit transform-based motion estimation scheme to reduce the computational load of the motion estimation process. Furthermore, the kernel used to obtain the one-bit images is simplified. Experimental results show significant reduction of the number of average search points, with only a slight loss in motion estimation accuracy.

Optimal Post-Process/In-Loop Filtering for Improved Video Compression Performance

This paper presents a novel optimal filtering approach that can be integrated into video compression schemes to improve video compression performance. In the proposed approach the encoder computes the coefficients of a linear filter in an optimal way, so as to minimize the squared error between the original frame and the filtered reconstructed frame. The encoder then multiplexes the filter coefficients into the bit-stream for decoder access. Reconstructed image frames are filtered at the decoder using optimal filter coefficients to obtain improved image frames. The optimal filtering approach is evaluated in the form of a post-process filter as well as in the form of an in-loop filter. It is shown using H.263+ and H.264/AVC that the proposed approach improves video compression performance of standard compression schemes.

Truncated graycoded bit-plane matching based motion estimation and its hardware architecture

This paper proposes an efficient low bit-depth representation based motion estimation approach which is particularly suitable for low-power consumer electronics devices. In the proposed approach motion estimation is carried out using bit truncated gray-coded image pixels. The corresponding hardware architecture is also designed and presented in this paper to show the effectiveness of the proposed approach. It is shown that the proposed approach provides improved motion estimation accuracy compared to conventional bit-truncation based approaches that are directly applied to binary coded pixel values. The proposed approach uses simple Gray-coding, that has very low-complexity and can be applied on a pixel-by-pixel basis. Hence, the comparatively more complex transformation processes required in one bit-transform or two-bit transform based low bit-depth representation ME approaches are avoided. Experimental results show that the proposed approach also outperforms such low bit-depth representation based motion estimation methods previously presented in the literature, in terms of motion estimation accuracy.

An all binary sub-pixel motion estimation approach and its hardware architecture

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices.

Parameter Embedding Mode and Optimal Post-Process Filtering for Improved WDCT Image Compression

The warped discrete cosine transform (WDCT) has been shown to improve the compression performance compared to standard DCT for image compression at high bit rates. In the proposed approach, the WDCT parameters are embedded into the transform coefficients for low bit rates in the form of a watermark to avoid the WDCT parameter side information overhead, improving the compression performance for low bit rates. Furthermore, optimal postprocess filtering, with filter coefficients being determined at the encoder and multiplexed into the bit stream, is proposed to improve the quality of the decoded image through postprocess filtering at the decoder. It is shown that a significant gain in quality can be achieved by the postprocess filtering. As optimal postprocess filtering is utilized, the need of a deblocking filter for low bit rates is finally evaluated to improve the statistical quality and visual appearance.

Single sub-image matching based low complexity motion estimation for digital image stabilization using constrained one-bit transform

A fast motion estimation approach based on single sub-image bit-plane matching for low complexity image stabilization is presented in this paper. The recently proposed one-bit transform (IBT) based motion estimation method for digital image stabilization which employs multiple sub-images has lower computational complexity, however the motion estimation accuracy is relatively low. Single sub-image matching proposed in this paper enhances motion estimation performance without causing additional computational load. Furthermore, the multiplication operation required for IBT is avoided using a new kernel. The recently proposed constrained IBT (C-IBT) that restricts pixels with values adjacent to the transform threshold is employed to increase performance at the cost of a slightly higher computational load. Experimental results show that the proposed approach outperforms other sub-image based approaches

Polyphase downsampling based multiple description image coding using optimal filtering with flexible redundancy insertion

In this paper, a novel multiple description image coding scheme is proposed to facilitate the transmission of images over unreliable networks. The target is to minimize the received image distortion over error prone channels. The proposed method is based on adding redundancy to multiple descriptions coding structure to increase correlation between descriptions. The novelty of the paper is that optimal reconstruction filter coefficients are obtained, that will be used to combine the multiple descriptions in an optimal way, based on least squares minimization of the reconstruction error. It is shown that the proposed method provides better results compared to existing approaches in the literature.