Anindya Poddar

Thermal characterization of stacked-die packages

Thermal characterization for multi-chip packages is a complicated process. Unlike the single-chip package, for which thermal resistance like /spl Theta//sub JA/ can be easily defined and measured, the presence of multiple heat sources in multi-chip packages makes the definition of thermal resistance impossible. In addition, multiple chip temperature typically needs to be measured at various power level combinations. In this paper, we studied a simple way to derive those chip temperatures by using the thermal resistance data from the equivalent single-chip packages. Our study is based on a comprehensive thermal evaluation of multi-chip packages. These packages contain 2 thermal test dice in a stacked fashion. Test samples were exclusively built based on 4 popular packaging types. Junction temperatures and board temperatures under standard JEDEC environment were measured using the Electrical Method and were correlated with the finite element-based detailed models. Based on an idealization of the heat transfer process, we derived a set of simple equations for approximating the junction and the board temperatures of stacked die packages. The only major input these equations require is the thermal resistance values of the equivalent single-chip packages, which are in general available. Therefore, no additional tests or simulations will be needed. In terms of accuracy, the new equations yielded promising results in most test cases although performance degradation does appear at certain package and boundary condition combinations.

Analytical and Experimental Characterization of Bonding Over Active Circuitry

Placing active circuitry directly underneath the bond pads is an effective way to reduce the die size, and hence to achieve lower cost per chip. The main concern with such design is the possible mechanical damage to the underlying circuitry during the wire bonding process. For example, the initial bond force and subsequent ultrasonic vibration may cause cracks within the dielectric layer. The cracks can penetrate through the active circuitry underneath, resulting in electrical failures to the silicon device. In this paper, a finite element based methodology was developed to study the stress behavior of bond pad structures during thermosonic wire bonding. The focus of our analysis is on dielectric layer crack, which was the dominant failure mode observed. The finite element (FE) model is 3-D based and contains the wire ball, the bond pad, and the underpad structure. The model was subjected to various bond force/ultrasound conditions, and the stresses were compared with the percentage of cracked pads in the real life bonding experiments. By using the volume-averaged, incremental first principal stress at the dielectric layer as the stress criterion, we achieved a reasonably good correlation with the experiments. In addition, we found that the dynamic friction at the bond interface is critical in stress distributions at the bond pad. Based on this, we have provided an explanation on how stresses progress during a typical bond force. Furthermore, the stress progression pattern was shown to correlate well with the different crack pattern. The FE model established a baseline upon which more designs with bonding over active circuitry can he analyzed and evaluated for crack resistance to thermosonic wire bonding.

Over pad metallization for high temperature interconnections

Electrolytic CuNiAu over pad metallization (OPM) was qualified for high temperature gold wire bonding applications. Stability of the CuNiAu OPM metal stack was tested through extreme conditions, i.e.: ambient temperature 250 °C up to 4000 hours, with satisfactory results. Reliability of CuNiAu OPM was then confirmed in series of tests with ambient temperature up to 175 °C, such as high temperature storage life (HTSL), highly accelerated stress test (HAST) and temperature cycle (TMCL), along with A10.5%Cu bond pad alloy as reference. The CuNiAu OPM test groups showed no functional failure and no change of failure mode in wire bond bump shear test — all samples exhibited the favorable bump shear mode. The reference A10.5%Cu group, on the other hand, showed degrading bump shear failure mode besides a few ATE test failures. Detailed failure analysis confirmed the integrity of OPM-gold wire bond interface, while revealing interfacial voids induced bump lift type of failure mode in the reference group. Good wafer sorting yield on CuNiAu OPM can be achieved with proper selection of probe type and materials. Wire bond optimization was also necessary to accommodate the unique electro-plated OPM topograph. Wafer handling has to be extra careful in order not to scratch the gold topped bumps that stands 5μm above the wafer passivation surface. Details are to be discussed in the following sections.

Effect of pad stacks on dielectric layer failure during wire bonding

Mechanical failure of the dielectric layer induced by the stresses during wire bonding processes is of concern for design requirements placing active circuitry directly underneath the bond pad. An effective way to avoid dielectric layer cracking is to optimize the multi-layered pad stack structures. In this paper, the effect of pad stack structures on dielectric layer cracks is studied using experimental characterization and FEM analysis. A 3-D FEM model is proposed based on a qualitative analysis of the wire bonding process and typical dielectric layer cracks observed from experiments. In the FEM model, the boundary conditions, loading, mesh and failure criterion are carefully determined so to be most computationally-efficient. The maximum in-plane normal stress range, Deltasigma1, is proposed here due to the brittleness of the thin dielectric layers and cyclic loading during the wire bonding process. The FEM model is validated by good correlations with real test data