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Featured researches published by L. Nguyen.


IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A | 1995

Optimization of copper wire bonding on Al-Cu metallization

L. Nguyen; David McDonald; Anselm R. Danker; Peter Ng

This paper reports the successful implementation of copper wire ball bonding for selected TO-220 devices on a high volume commercial scale. Since August 1992, copper wire bonding has been used in production at National Semiconductor Corp. The development of copper wire ball bonding involves a three-prong approach: optimum pad metal composition, modifications to the wire bonder and optimization of the assembly parameters. the critical material parameter is bond pad hardness. This needs to be above a critical threshold value to avoid silicon cratering. The metal composition best suited for the wire bonding process is sputtered Al-Cu(2%). Typical production yields of 99.8% at lead bond are obtained with 1.5 mil (37.5 /spl mu/m) copper wires, with ball shear and wire pull averaging 100/spl plusmn/20 gms and 15/spl plusmn/2 gms, respectively. Five issues related to copper wire bonding of TO-22 power IC packages are discussed: 1) typical bonding failure modes; 2) the relation between bond pad composition and hardness; 3) the influence of the metal deposition systems; 4) the optimization of bonding conditions; 5) the reliability of the copper wire bonded devices. >


electronic components and technology conference | 1995

A new criterion for package integrity under solder reflow conditions

L. Nguyen; K.L. Chen; J. Schaefer; A.Y. Kuo; G. Slenski

Moisture-induced package cracking during the solder reflow process is a critical reliability problem with plastic integrated circuit (IC) packaging. Such cracking, typically referred to as popcorning, occurs from the evaporation and expansion of moisture absorbed by the hygroscopic epoxy molding compound (EMC). Although the device may still test functionally good after assembly, the cracks introduce a path for ionic contaminants to infiltrate into the package and cause corrosion-induced failures. The following mechanism is proposed. Moisture in the outer and hotter portion of the EMC vaporizes first, while most of the moisture in the inner and cooler portion of the EMC remains in the liquid phase. Some localized hydrostatic pressure can become positive, generating subsequently high pressure that can initiate and propagate cracks. This paper reports the effects of the localized vaporization, which is a major albeit still neglected loading mode contributing to popcorning failures. For simplicity, only two-dimensional modeling problems are investigated in this phase of the study. Numerous moisture-induced cracking experimental data are examined to provide correlation with the proposed failure criterion. Among the parameters studied are package form factors, die-to-die pad ratio, molding compounds, moisture content, and heating profiles.


electronic components and technology conference | 1993

Reactive flow simulation in transfer molding of IC packages

L. Nguyen

Transfer molding is currently the most widely used process for encapsulating integrated circuits. Although the process was introduced over 20 years ago, generating billions of parts each year, it is far from being optimized. With each new mold, molding compound, and device, lengthy and expensive qualification runs have to be performed to minimize defects ranging from incomplete fill, part-non-uniformity, wire sweep, and voids. Testing is carried out more on a trial-and-error basis than by following some heuristic process guidelines. This paper describes how reactive flow simulation can be applied to transfer molding to yield acceptable design and processing parameters. The non-isothermal filling of non-Newtonian reactive epoxy molding compounds in a multi-cavity mold is analyzed and modeled. Analysis is conducted to investigate the influence of process deviations on the final molded profile. The rheological and kinetic behavior of a low-stress compound used for encapsulating ICs is studied.<<ETX>>


intersociety conference on thermal and thermomechanical phenomena in electronic systems | 1992

Effect of mold compound thermal conductivity on IC package thermal performance

M. Michael; L. Nguyen

The authors discuss the effects of varying the thermal conductivity of epoxy molding compounds on the thermal behavior of plastic IC packages. Thermal conductivity values were estimated for various filler types (fused and crystalline silica, aluminum oxide, aluminum and boron nitride, silicon carbide, and diamond), sizes, and distribution. Values for the resulting composites were used in determining the effectiveness of the compound in dissipating heat away from the package. Finite-element simulation was also used to predict the thermal performance of three different surface mount configurations, namely, SOIC 8-L, 16-L wide, and 24-L wide. The combined effects of the thermally enhanced mold compounds and enhanced leadframe designs were investigated. Natural convection and forced convection heat transfer simulation determined the effectiveness of the high thermal conductivity encapsulants under different application conditions.<<ETX>>


electronic components and technology conference | 1994

Effects of die coatings, mold compounds and test conditions on temperature cycling failures

L. Nguyen; Steven A. Gee; Martin R. Johnson; Herb E. Grimm; Hector Berardi; Randy L. Walberg

When a plastic package is subjected to repeated thermal excursions such as during thermal cycling or thermal shock, progressive damage to the silicon die occurs. Damage can be initiated in the form of interfacial delamination accompanied by passivation cracking, and subsequently, by dielectric fracture that may ultimately lead to device failure. The extent of damage depends on the interaction between the various components in the package. In this study, thermal cycling of PLCC packages indicated that the die design configuration, the nature of the coating and its thickness, the formulation of the molding compound, the preconditioning of the packages, and the thermal excursion conditions all govern the electrical failure rates observed. Thus, careful selection of the proper combination of parameters can offer improved device reliability. >


Journal of Electronic Materials | 2012

Maximum-Entropy Principle for Modeling Damage and Fracture in Solder Joints

D. Chan; Ganesh Subbarayan; L. Nguyen

A maximum-entropy fracture model (MEFM) is derived from concepts of information theory and statistical thermodynamics. Exploiting the maximum-entropy principle enables life predictions for a structure in the presence of microstructural uncertainty. This single-parameter model relates the probability of fracture to accumulated entropic dissipation at a given material point. Using J2 plasticity and equilibrium thermodynamics, entropic dissipation is related to inelastic dissipation. We demonstrate the MEFM by extracting the single damage accumulation parameter for Sn-3.8Ag-0.7Cu solder through cyclical fatigue testing. We then apply the model with the single parameter to numerically predict, in three dimensions, crack initiation and growth in Sn-3.8Ag-0.7Cu solder joints of a wafer-level chip-scale package (WLCSP). The simulated crack fronts are validated against experimentally observed crack fronts obtained by testing 64 packages under conditions identical to those used in the simulations. The model is shown to accurately predict the geometrical profile of the observed crack fronts, and the number of cycles corresponding to the observed crack profile to within 10% of the measured number of cycles.


electronic components and technology conference | 2000

A manufacturing perspective of wafer level CSP

L. Nguyen; Nikhil Vishwanath Kelkar; H. Takiar

The micro SMD package, a wafer level Chip Scale Package (CSP), was successfully introduced by National Semiconductor about two years ago for portable wireless applications where weight, thin form factor, and board space savings are as critical as increased functionality. The package provides a matrix interconnect layout at 0.5 mm pitch, does not require underfill, and leverages standard surface mount assembly techniques. This paper will evaluate the pros and cons of packaging this wafer level CSP against a conventional leaded package and a traditional CSP.


electronic components and technology conference | 1992

Effects of die pad anchoring on package interfacial integrity

L. Nguyen; M.M. Michael

The effects of anchoring the die pad to the epoxy molding compound to improve the package interfacial integrity are addressed. The designs considered varied from simple circular holes dispersed at the four corners of the die pad to longer slots distributed along the periphery of the die. 3-D finite element models were constructed to simulate the residual stress profiles within the various molded configurations. Interfacial delamination was artificially induced at selected locations of the die pad by nodal decoupling. The simulation results were compared with acoustic tomograph scans of the packages to assess any correlation between the predicted high stress profiles and the extent of delamination observed. The introduction of an anchor in the die pad provided various degrees of stress relief to the silicon die, depending on the anchor geometry. Although the effects were localized, the ensuing stress reduction was sufficient in some cases to avoid the initiation of delamination. Finite-element results also pinpointed other areas of high stress concentration, which acted as potential sites where delamination could initiate and propagate. Based on these results, design criteria were formulated to dictate the most efficient pattern of holes and slots that would provide the best anchoring properties to the molding compound.<<ETX>>


electronic components and technology conference | 1994

Leadframe designs for minimum molding-induced warpage

L. Nguyen; K.L. Chen; P. Lee

The current packaging trend toward thinner packages has pushed the leadframe manufacturing technology to the limits. For instance, with Ultra Thin Small Outline Packages (UTSOPs), the total form factor is less than 0.5 mm thick, which is about twice the thickness of the typical leadframe used in current standard IC packages. Thus, the leadframe must be scaled down appropriately with the rest of the package components. The thinner leadframe stock brings a host of handling difficulties. Most important of all is the bending and twisting of the leadframes caused by molding induced stresses. The resulting deformation affects the subsequent post-molding steps such as trim and form, and may seriously increase the production yield loss due to lead non-coplanarity. This study addresses the manufacturing and design issues involved with minimizing these molding-induced stresses. Through a combination of good control on the process parameters (e.g., post-molding handling, cooling, deflash procedures, etc.) and leadframe designs (e.g., package relative positioning within the leadframe strips, relief holes and slots, strengthened support strips, etc.), leadframe warpage from thermomechanical stresses can be reduced. Warpage predictions from finite element simulation will be presented for various leadframe designs in this paper.<<ETX>>


electronic components and technology conference | 2007

Fatigue Crack Growth and Life Descriptions of Sn3.8Ag0.7Cu Solder Joints: A Computational and Experimental Study

D. Bhate; D. Chan; Ganesh Subbarayan; L. Nguyen

The need for predicting fatigue life in solder joints is well appreciated at the present time. Currently, however, there are very few experimentally validated material parameters for popular SnAgCu alloys. Furthermore, the validity of Coffin-Manson life models, being empirical, also needs to be explored for these alloys which creep in a manner significantly different from SnPb solder alloys. In this paper, we present a modeling approach inspired by cohesive zone theory of modern fracture mechanics and Weibull distributions of material failure. The approach relies on the accurate estimation of inelastic strains at the crack tip estimated through finite element analysis, which are then used to make decisions on crack propagation. Like most popular cohesive zone models, the modeling approach presented here requires the estimation of two parameters. Unlike most cohesive zone models however, no special elements are needed in the finite element model and estimation of the parameters is more straightforward. We demonstrate the applicability of the modeling approach via the simulation of fatigue crack growth in Sn3.8Ag0.7Cu solder joints subjected to anisotropic thermal cycling. Anisotropic thermal cycling conditions were created experimentally using a simulated power cycling testing device and fatigue crack fronts were tracked at different life cycles using traditional dye-and-pry methods. The experiments were repeated for varying temperature profiles. Experimental results were coupled with numerical analysis to obtain fracture parameters for Sn3.8Ag0.7Cu. The model and the parameters were then validated by verifying their predictive ability against a variety of temperature profiles. In a separate study, the authors have developed a time hardening creep model for describing the behavior of Sn3.8Ag0.7Cu. The time hardening model accounts for primary and secondary creep and does not restrict itself to the assumption of steady state creep. The need for accurate estimation of inelastic strains in the finite element model is thus met using a valid constitutive model to describe solder creep behavior. The ability of the model to predict three dimensional crack fronts for a variety of fatigue loading environments, with sufficient accuracy, is a key result of this work.

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K.L. Chen

National Semiconductor

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Peter Deane

National Semiconductor

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A. Prabhu

National Semiconductor

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A.S. Lu

National Semiconductor

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