Anissa Sghaier

FPGA implementation of filtered image using 2D Gaussian filter

Image filtering is one of the very useful techniques in image processing and computer vision. It is used to eliminate useless details and noise from an image. In this paper, a hardware implementation of image filtered using 2D Gaussian Filter will be present. The Gaussian filter architecture will be described using a different way to implement convolution module. Thus, multiplication is in the heart of convolution module, for this reason, three different ways to implement multiplication operations will be presented. The first way is done using the standard method. The second way uses Field Programmable Gate Array (FPGA) features Digital Signal Processor (DSP) to ensure and make fast the scalability of the effective FPGA resource and then to speed up calculation. The third way uses real multiplier for more precision and a the maximum uses of FPGA resources. In this paper, we compare the image quality of hardware (VHDL) and software (MATLAB) implementation using the Peak Signal-to-Noise Ratio (PSNR). Also, the FPGA resource usage for different sizes of Gaussian kernel will be presented in order to provide a comparison between fixed-point and floating point implementations.

A hardware-software co-designed AES-ECC cryptosystem

Securing data transfer is a primary need for all embedded systems. The AES-ECC hybrid cryptosystem combines advantages of the Advanced Encryption Standard (AES) to accelerate data encryption and the Elliptic Curve Cryptography (ECC) to secure the exchange of symmetric session key. In this paper, we present an improved AES-ECC system using a co-design approach where AES runs on NIOS II softcore and ECCs scalar multiplication is implemented as a hardware accelerator. The proposed system relies on optimizations of both AES (MixColumn/InvMiColumn operation) and ECC (Point Addition/Doubling layer). The implementation on a Cyclone IV FPGA uses 11% of total logic elements, 9% of total combinatorial functions and 7% of total memory. It runs at a frequency of 157.63 MHz and consumes 166.67 mW. A comparison with similar works shows that the proposed system provides an interesting trade-off between speed and area occupation.

Proposed unified 32-bit multiplier/inverter for asymmetric cryptography

Arithmetic in GF(2n) finite fields in asymmetric cryptography is the key of an efficient cryptosystems implementation. Thus, cryptosystems based on algebraic curves such as Hyper/Elliptic curves (ECC,HECC) and Pairings need a big number of arithmetic operations. They required several GF(2n) inversions and multiplications which are the most time and area consuming operations. This paper describes a hardware architecture for computing both modular multiplication and modular inversion in GF(2n) finite fields, based on a Modified Serial Multiplication/Inversion (MSMI) algorithm. The algorithm is suitable for both hardware implementations and software implementations. The proposed design performs 8-bits, 16-bits, 32-bits or 64-bits modular multiplication or inversion. Our design was modeled using VHDL and implemented in the Xilinx FPGAs Virtex6. Implementation results prove that our MSMI uses only 219 FPGA slices, it achieves a maximum frequency of 150 MHz and it computes 163-bits modular multiplication in 4.21 µ secs.

Fast hardware implementation of ECDSA signature scheme

Elliptic Curve Digital Signature Algorithm (ECDSA) is a variant of Digital Signature Algorithm (DSA). Thus, ECDSA is the most suitable in environments where processor power and storage are limited such as smart cards and wireless devices. In this paper, we present ECDSA hardware implementation over Koblitz subfield curves with 163-bit key length recommended by the NIST. To perform it, we need three main operations which are key generation by the use of ECC (Elliptic Curve Cryptography) scalar multiplication, signature generation based on Secure Hash Standard 2(SHA2) and signature verification. All modules are implemented on a Xilinx Virtex 5 ML 50 FPGA platform, they require respectively 9670 slices, 2530 slices, and 18504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, we implemented our design on an ASIC CMOS 45 nm technology, it requires 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW).

Efficient software implementation of RNS-montgomery modular multiplication for embedded system

Recently, a lot of progress has been made in the implementation of asymmetric cryptography such that RSA or ECC (Elliptic Curve Cryptography) in both hardware and software. The Residue Number Systems (RNS) offer, many features make it very useful in cryptographic applications. Since the modular multiplication is the main operation, in this paper, we describe a Montgomery modular multiplication algorithm based on RNS. Then we implemented our design in TM i3 CPU, it computed the modular multiplication in only 9 ms (latency) and achieving maximum throughput of 528.

Efficient software implementation of the final exponentiation for pairing

Pairing-based cryptography has got a lot of attention the last years, since the proposition of the tripartite key exchange. The best type of pairing is optimal ate pairing over Barreto-Naehrig curves which are based on two steps: Miller Loop and final exponentiation. Most of the researches were done for the Miller Loop. In this paper, we present the different methods for computing the hard part of the final exponentiation of optimal ate pairings based on a hard mathematical study. Using a comparative study based on the temporary number and memory resources, we will choose the best method to be then implemented in Matlab Software. Thus, the best one is Devigili et al. method presenting a reduced complexity and required number of registers.

Proposed efficient arithmetic operations architectures for Hyperelliptic Curves Cryptosystems (HECC)

Because it offers several benefits over other public-key cryptosystems much effort are done to make Hyper Elliptic Curve Cryptosystems (HECC) more practical, such as RSA, it offers a comparable level of security with a smaller key size. For this reason, HECCs can be used in embedded environments where speed, energy, power, chip and memory area are constrained. However, HEC use a complex mathematical background, so its difficult to be implemented on hardware. They can be defined over real numbers, complex numbers and any other field. So we need arithmetic operations (addition, subtraction, multiplication and division) which have much application in cryptography and coding theory. We have to note that the overall performance of HECC is mainly determined by the speed of arithmetic operations. The most algorithms that manipulate these operations use polynomial coefficients in base 2 and they are defined over finite fields. But, the problem is clearly viewed over real field and simple to be presented. Arithmetic operations are based on the complexity of a mathematical problem, and to have an optimized architecture we need to optimize arithmetic operations. In this paper we describe a high performance, area efficient implementation of arithmetic operations in HECC over real field and a new design methodology is presented. The proposed architectures operations are implemented in FPGA.