Medien Zeghid

A Reconfigurable Implementation of the New Secure Hash Algorithm

The main applications of the hash functions are met in the fields of communications integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. We propose a configurable secure hash algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGA-based implementations. A fastest data throughput is achieved by our optimized algorithm

Performance evaluation and design considerations of lightweight block cipher for low-cost embedded devices

In this paper we present the design considerations of lightweight encryption algorithm. Our aim is to demonstrate how to achieve lightweight block ciphers efficient software performance for low-resource embedded devices. Several lightweight block ciphers are proposed; we selected the most recent and suitable for low-resource embedded systems such as RFID tags. In this work, we analyzed the software implementation of lightweight block ciphers using FELICS (Fair Evaluation of Lightweight Cryptographic Systems) a benchmarking framework which computes execution time, RAM consumption and ROM occupation on two largely used devices: 8-bit AVR microcontroller and 16-bit MSP microcontroller. Using the same evaluation conditions, we selected the most suitable ciphers for low-resource devices.

A scheduling approach for packet-switched on-chip networks

Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.

Lightweight Encryption Algorithm Based on Modified XTEA for Low-Resource Embedded Devices

The number of resource-limited wireless devices utilized in many areas of Internet of Things is growing rapidly; there is a concern about privacy and security. Various lightweight block ciphers are proposed; this work presents a modified lightweight block cipher algorithm. A Linear Feedback Shift Register is used to replace the key generation function in the XTEA1 Algorithm. Using the same evaluation conditions, we analyzed the software implementation of the modified XTEA using FELICS (Fair Evaluation of Lightweight Cryptographic Systems) a benchmarking framework which calculates RAM footprint, ROM occupation and execution time on three largely used embedded devices: 8-bit AVR microcontroller, 16-bit MSP microcontroller and 32-bit ARM microcontroller. Implementation results show that it provides less software requirements compared to original XTEA. We enhanced the security level and the software performance.

An Efficient Spectral Amplitude Coding (SAC) Technique for Optical CDMA System using Wavelength Division Multiplexing (WDM) Concepts

This article introduces an improved method for Optical Code Division Multiple Access system (OCDMA). In this scheme, a hybrid technique is used in which Wavelength Division Multiplexing (WDM) is merged with Spectral Amplitude Coding (SAC) to efficiently diminish Multiple Access Interference (MAI) and alleviate the impact of Phase Induced Intensity Noise (PIIN) appearing in photo-detecting process. The proposed technique SAC-OCDMA/WDM MP (SW-MP) is implemented by using Matrix Partitioning (MP) code family, which is constructed via merging mathematics sequence and algebraic approaches. The key notion is to create the code patterns in SAC domain, then diagonally replicate it in the wavelength domain as blocks which preserves the same code patterns of a given code weight. The SW-MP code family preserves convenient code length property which gives flexibility in transmitter-receiver design. It is reported that the proposed scheme has potential to remove MAI proficiently and improve the system performance significantly.

A hardware-software co-designed AES-ECC cryptosystem

Securing data transfer is a primary need for all embedded systems. The AES-ECC hybrid cryptosystem combines advantages of the Advanced Encryption Standard (AES) to accelerate data encryption and the Elliptic Curve Cryptography (ECC) to secure the exchange of symmetric session key. In this paper, we present an improved AES-ECC system using a co-design approach where AES runs on NIOS II softcore and ECCs scalar multiplication is implemented as a hardware accelerator. The proposed system relies on optimizations of both AES (MixColumn/InvMiColumn operation) and ECC (Point Addition/Doubling layer). The implementation on a Cyclone IV FPGA uses 11% of total logic elements, 9% of total combinatorial functions and 7% of total memory. It runs at a frequency of 157.63 MHz and consumes 166.67 mW. A comparison with similar works shows that the proposed system provides an interesting trade-off between speed and area occupation.

Proposed unified 32-bit multiplier/inverter for asymmetric cryptography

Arithmetic in GF(2n) finite fields in asymmetric cryptography is the key of an efficient cryptosystems implementation. Thus, cryptosystems based on algebraic curves such as Hyper/Elliptic curves (ECC,HECC) and Pairings need a big number of arithmetic operations. They required several GF(2n) inversions and multiplications which are the most time and area consuming operations. This paper describes a hardware architecture for computing both modular multiplication and modular inversion in GF(2n) finite fields, based on a Modified Serial Multiplication/Inversion (MSMI) algorithm. The algorithm is suitable for both hardware implementations and software implementations. The proposed design performs 8-bits, 16-bits, 32-bits or 64-bits modular multiplication or inversion. Our design was modeled using VHDL and implemented in the Xilinx FPGAs Virtex6. Implementation results prove that our MSMI uses only 219 FPGA slices, it achieves a maximum frequency of 150 MHz and it computes 163-bits modular multiplication in 4.21 µ secs.

A Format-Compliant Selective Encryption Scheme for Real-Time Video Streaming of the H.264/AVC

H.264 video coding standard is one of the most promising techniques for the future video communications. In fact, it supports a broad range of applications. Accordingly, with the continuous promotion of multimedia services, H.264 has been widely used in real-world applications. A major concern in the design of H.264 encryption algorithms is how to achieve a sufficiently high security level, while maintaining the efficiency of the underlying compression process. In this paper a new selective encryption scheme for the H.264 standard is presented. The aim of this work is to study the security of the H.264 standard in order to propose the appropriate design of a hardware crypto-processor based on a stream cipher algorithm. Since the proposed cryptosystem is mainly dedicated to the multimedia applications, it provides multiple security levels in order to satisfy the requirements of various applications for different purposes while ensuring higher coding efficiency. Different performance analyses were made in order to evaluate the new encryption system. The experimental results showed the reliability and the robustness of the proposed technique.

Fast hardware implementation of ECDSA signature scheme

Elliptic Curve Digital Signature Algorithm (ECDSA) is a variant of Digital Signature Algorithm (DSA). Thus, ECDSA is the most suitable in environments where processor power and storage are limited such as smart cards and wireless devices. In this paper, we present ECDSA hardware implementation over Koblitz subfield curves with 163-bit key length recommended by the NIST. To perform it, we need three main operations which are key generation by the use of ECC (Elliptic Curve Cryptography) scalar multiplication, signature generation based on Secure Hash Standard 2(SHA2) and signature verification. All modules are implemented on a Xilinx Virtex 5 ML 50 FPGA platform, they require respectively 9670 slices, 2530 slices, and 18504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, we implemented our design on an ASIC CMOS 45 nm technology, it requires 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW).

Efficient software implementation of RNS-montgomery modular multiplication for embedded system

Recently, a lot of progress has been made in the implementation of asymmetric cryptography such that RSA or ECC (Elliptic Curve Cryptography) in both hardware and software. The Residue Number Systems (RNS) offer, many features make it very useful in cryptographic applications. Since the modular multiplication is the main operation, in this paper, we describe a Montgomery modular multiplication algorithm based on RNS. Then we implemented our design in TM i3 CPU, it computed the modular multiplication in only 9 ms (latency) and achieving maximum throughput of 528.