Anjan Chakravorty

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design.

Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self-Heating

A physics-based compact model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors including impact ionization, subsequent snapback (SB), and self-heating (SH) is presented. It is observed that the SB effect is caused by the turn-on of the associated parasitic bipolar transistor. The model includes the effect of device SH using resistive thermal networks for each region. Comparisons of modeling results with device simulation data show that, over a wide range of bias voltages, the model exhibits excellent accuracy without any convergence problem.

Compact Modeling of High Frequency Correlated Noise in HBTs

A compact model solution, consistent with the system theory for correlated base and collector shot noise sources, is derived and implemented in the bipolar transistor model HICUM using Verilog-A. Compiled (with Tiburon) Verilog-A model is simulated using ADS 2004A and the results are tested against measured noise parameters for high-frequency (fT at 150 GHz) SiGe HBTs. Very good agreement between simulated and measured data is obtained

Modeling Nonquasi-Static Effects in SiGe HBTs

The shortcomings of quasi-static and partitioned charge-based models are quantitatively demonstrated for 1-D SiGe heterojunction bipolar transistors. This points out the need to include higher order frequency-dependent terms, i.e., nonquasi-static effects in the model. Three different implementation-suitable modeling approaches are presented with associated formulations. Detailed comparison with the original theory is carried out to show the different levels of achievable accuracy of the formulated models. Circuit simulator implementations, parameter extractions, and validations of the models with device simulation results are also carried out. Frequency- and time-domain small-signal modeling results are found to be consistent and provide a high level of accuracy. For two selected cases among the various modeling approaches, results of large-signal transient switching are presented, showing excellent agreement with device simulation.

Compact modeling of SOI-LDMOS including quasi-saturation effect

This paper presents a physics-based compact dc model for high voltage silicon on insulator lateral double diffused MOS (SOI-LDMOS) transistor, assuming uniform doping for the channel. It uses MM20 model for the channel and drift region under the thin gate oxide, and proposes a new model for the drift region under the field oxide. This model shows that the current at higher gate voltages in SOI-LDMOS, is limited by the velocity saturation in the drift region under the field oxide, which determines the device behavior in the quasi-saturation region. The model exhibits high level of accuracy over wide bias ranges.

Analytic Estimation of Thermal Resistance in HBTs

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors

In this paper, we report an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (SOI-LDMOS) transistors. First, a model of a 2-D SOI resistor under velocity saturation is developed, which is subsequently incorporated into the drift region of an LDMOS transistor to predict the quasi-saturation effect. The gate-voltage dependence of the quasi-saturation current is also modeled. Second, we propose a new nodal charge model to describe the dynamic behavior of the device. Comparisons of modeling results with device simulation data show that the proposed model is accurate over a wide range of bias. Scalability of the model with respect to the length of the drift region under the field oxide is also demonstrated. Finally, the model is validated under device self-heating conditions and by comparing it with the experimental data.

Design of Novel High- \(Q\) Multipath Parallel-Stacked Inductor

In this brief, we present a novel multipath parallel-stacked inductor structure that significantly reduces the current crowding effects. Both the metal layers of the parallel stack are divided into multiple segments and crossovers are provided midway of each turn to steer the current in such a way that all its segments have equal path lengths. Following the multipath architecture, prototype inductor structures are fabricated in a 0.18-μm high-resistivity silicon-on-insulator technology using a dual thick metal stack process. Measurements show >30% improvement in quality factor (Q) with the proposed architecture when compared with a standard parallel-stacked inductor. The Q improvement achieved by the proposed inductor structure is shown to increase with the spiral thickness making them suitable for both radio frequency circuits and DC-DC buck converters without having to use magnetic materials. Via resistance is shown to limit the Q improvement possible with proposed inductor configuration.

Modeling high-frequency noise in SiGe HBTs using delayed minority charge

Based on delayed minority charge high frequency correlated noise in silicon germanium heterojunction bipolar transistor is modeled. Following system theory, the formulated model equations are accurately implemented in Verilog-A using four extra nodes. Results show excellent agreement with numerically simulated data. Simplified model versions are also implemented and tested. Relation between high-frequency correlated noise and non-quasi-static effect is identified through delayed minority charge.

High Density Solenoidal Series Pair Symmetric Inductors and Transformers

A high density symmetric inductor using a novel combination of solenoidal wound series stacked spirals is proposed in this paper. Series stacking in the individual sections increases overall inductance density, while solenoidal winding pushes the quality factors (Q) to higher frequencies. The proposed inductor achieves more than 65% improvement in peak-Q value and 100% higher peak-Q frequency and self resonance frequency, while occupying 20% lesser area when compared with a standard symmetric inductor with crossovers. Implemented in a high resistivity 0.18 μm CMOS silicon-on-insulator process with dual-thick metal stack, the proposed inductor achieves 70-nH inductance and a Q of 11.3 operating at 1.6 Gilz within 250 × 250 μm2 area. This translates to a record figure-of-merit of 12.2, which is highest in air core symmetric inductor literature. Further, the proposed inductor configuration is extended to realize a planar transformer with very high turns ratio of 9.25 using only two metals.