Ankesh Jain

Analysis and Design of a High Speed Continuous-time

We apply the “assisted opamp technique” to the design of a 1 GS/s single-bit continuous-time ΔΣ modulator (CTDSM) that achieves 10 bit resolution in 15.625 MHz bandwidth. The enhanced linearity and speed of the first integrator of the modulator, necessitated by single-bit operation, are obtained in a power efficient manner using opamp assistance. However, timing-skew between the feedback and assistant DAC currents can be a potential problem at high speeds. We analyze and give intuition for the effects of timing mismatch in such CTDSMs, and show that opamp assistance is quite robust to timing errors. Measurement results from an implementation in a 0.13 μ m CMOS process show that the modulator achieves a dynamic range of 67 dB in 15.625 MHz bandwidth while consuming 4 mW.

\Delta\Sigma

Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feedthrough effects. Experimental results from a test chip in 90 nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz.

Modulator Using the Assisted Opamp Technique

We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.

Characterization Techniques for High Speed Oversampled Data Converters

Characterizing wide band continuous-time ΔΣ modulators is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. Experimental results from a single-bit CTDSM operating at 4.4 GHz are given, demonstrating the efficacy of the technique.

A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback

We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.1