Shanthi Pavan

A Power Optimized Continuous-Time

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.

\Delta \Sigma

We examine noise due to clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators (CT-DSMs) employing nonreturn to zero (NRZ) feedback digital-to-analog converters (DACs). Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function (NTF) of the modulator. We show that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their passbands have lower jitter noise than maximally flat NTFs. We propose a design procedure that minimizes the sum of the quantization and jitter noise. The arguments regarding Delta Sigma analog-to-digital converters are extended to Delta Sigma DACs and measurement results are presented.

ADC for Audio Applications

The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 /spl mu/m CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm/sup 2/ and consumes less than 187 mW of power.

Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2.

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS process

The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.

Design Techniques for Wideband Single-Bit Continuous-Time

We present a simple, intuitive technique to compensate the loop filter transfer function for excess delay in low-pass continuous-time DeltaSigma modulators. Conventional methods of finding the appropriate filter coefficients to account for loop delay work in the z-domain, leading to cumbersome algebra. We show that the same objective can be accomplished entirely in the continuous-time domain, resulting in a procedure that lends itself to hand calculations, even for high order modulators. We derive closed-form expressions for the loop filter coefficients in modulators using nonreturn-to-zero and return-to-zero digital-to-analog converters. Simulation results confirming the theory are given.

\Delta\Sigma

We address the practical problem of determining the loop filter component values in a single-loop continuous-time delta sigma modulator. Conventional techniques to design center the converter to achieve a desired noise transfer function are cumbersome and not numerically stable. We present a robust procedure that can be used to determine the loop filter coefficients when real opamps (with finite gain, arbitrary Digital to Analog Converter (DAC) pulse, and multiple internal poles/zeros) are used. The method can also account for excess loop delay. We illustrate our technique with second-order low-pass and fourth-order bandpass examples.

Modulators With FIR Feedback DACs

We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of ldquoconstant capacitance scalingrdquo is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 times range. The filter core, designed in a 0.18-mum CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB.

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique

We present a completely analytical solution to a filter-comparator oscillator system, and verify it by macromodel simulations and experiment. We discuss the applications of this kind of oscillator in a vector-locked loop system for continuous time filter tuning. We also apply our solution to the operation of a resonant switched mode inverter.

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.