Maurits Ortmanns

A 232-Channel Epiretinal Stimulator ASIC

This paper presents the architecture and design of a stimulator ASIC for a visual prosthesis. The circuit employs fully wireless operation and features 232 channels with a maximum of 116 parallel stimulations. The architecture is separated into shared global functions and locally distributed stimulation functions. High tissue impedance of epiretinal stimulation sets the need for high-voltage output compliance, which is typically as high as 22.5 V in this implementation. For implantation-ready design, full testability has been achieved, full ESD protection was implemented, and novel safety features were realized in order to combine highly flexible operation with maximum innocuousness for the patient. The overall stimulator occupies 22 mm2 in a 0.35 HVCMOS technology.

A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.

A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants

This paper presents an integrated neural stimulator with highly efficient and flexible frontend which is intended for an epiretinal implant with 1024 electrodes. It features programmable stimulation pulse shapes, a high-voltage (HV) output driver with compliance monitor for supply voltage adaptation, active and passive charge balancers, and electrode impedance measurement. Area and power efficiency is achieved by global timing assignment and local amplitude control over a bus at the local stimulation units. Major power savings in the distributed digital control units are realized by implementing global and local clock gating. Two stimulator frontends have been fabricated in a 0.35 μm HVCMOS process. Each frontend features four demultiplexed outputs and consumes 0.2 mm2 core area. A maximum voltage compliance of 20 V is achieved and up to 1 mA of output current can be adjusted with up to 50 dB dynamic range. In vitro experimental results performed on a platinum black electrode in 0.9% saline solution are given.

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time sigma-delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD.

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.

An Active Approach for Charge Balancing in Functional Electrical Stimulation

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. This paper presents a new active approach for charge balancing using long-term offset regulation. Therefore, the electrode voltage is briefly monitored after each stimulation cycle and checked if it remains within a predefined voltage range. If not, an offset current is adjusted in order to track the biphasic current mismatch in upcoming stimulations. This technique is compared to a previously introduced active charge balancer as well as commonly used passive balancing techniques. Subsequently, the techniques are verified through experiments on a platinum black electrode in 0.9% saline solution.

A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications

In this paper, a fully CMOS integrated active AC/DC converter for energy harvesting applications is presented. The rectifier is realized in a standard 0.35 µm CMOS process without special process options. It works as a full wave rectifier and can be separated into two stages—one passive and one active. The active part is powered from the storage capacitor and consumes about 600 nA at 2 V supply. The input voltage amplitude range is between 1.25 and 3.75 V, and the operating frequency range is from 1 Hz to as much as several 100 kHz. The series voltage drop over the rectifier is less than 20 mV. Measurements in combination with an electromagnetic harvester show a significant increase in the achievable output voltage and power compared to a common, discrete Schottky diode rectifier. The measured efficiency of the rectifier is over 95%. Measurements show a negligible temperature influence on the output voltage between −40 °C and +125 °C.

An 8.5 mW Continuous-Time

This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the ΔΣ modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented ΔΣ modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm2 and has a power consumption of 8 mW, with an additional 0.02 mm2 and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.

\Delta \Sigma

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.

Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm2 and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.