Anna W. Topol

Three-dimensional integrated circuits

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Three-dimensional silicon integration

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures

In this paper, we describe several critical aspects of wafer scale or die level bonding to demonstrate: (1) low temperature bonding for planar layer interconnections; (2) low temperature bonding for non-planar layer sealing; (3) alignment and transfer of process sub-assemblies such as BEOL wiring, MEMS cavity or active device structures; and (4) integration methodology for fabrication of these layer stacks into 3D circuits and MEMS. We also show examples of how layer stacking protocols using wafer bonding technology provides a capability to integrate mixed materials and technologies potentially adaptable to many other applications. In addition, we demonstrate that in order to evaluate the influence of bonding on the electrical integrity of the transferred ICs, state-of-the art circuits, such as short channel length MOSFETs or ring oscillators, should be tested as they are most sensitive to environmental/processing changes.

Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits

Three-dimensional integration (3DI) is a very promising fabrication methodology for extending the CMOS technology roadmap. As such, it is critical to evaluate the capability of this technique to provide reliable interconnection between stacked circuit layers. Since one of potential approaches for 3DI is through use of Cu bonded interconnects, the viability of this process is evaluated in this paper. More specifically, the integrity of bonded Cu interconnects has been investigated as a function of pattern geometry and density, as well as bonding process parameters. It is found that a pattern density around or more than 13 % coupled with the application of a small down-force (~1000 N) prior to temperature ramping and followed by large down-force (~10000 N) during bonding gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and thermal reliability. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology

Transistor scaling with novel materials

Complementary metal-oxide-semiconductor (CMOS) transistor scaling will continue for at least another decade. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. Here we discuss the challenges and opportunities of transistor scaling for the next five to ten years.

High performance FDSOI CMOS technology with metal gate and high-k

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.

3D Fabrication Options for High-Performance CMOS Technology

The last several decades have seen an incredible increase in the functionality of computational systems. At its core, this capability has been driven by the scaling of semiconductor devices, from fractions of millimeters in the 1960s to tens of nanometers in today’s technologies. The scaling has enabled the number of transistors on a single chip to correspondingly grow at a geometric rate, roughly doubling every 18 months; a trend is that now referred to as Moore’s law [1]. The impact of this trend cannot be underestimated and the resulting increase in computational capacity has had major impacts on almost every facet of society. For this reason, there is a tremendous push to continue along these same trends. However, several serious roadblocks exist. The first is the limits to lithographic scaling. The second is that power densities will not allow reliable systems to be fabricated even if lithographic scaling could continue. Therefore, it becomes a big challenge to increase system performance. Three dimensional (3D) integration technologies offer the promise of increasing system performance even in the absence of scaling. However, the main advantages of 3D integration can be summed up as follows: (1) 3D decreases the interconnect distance between regions of a chip, decreasing wiring parasitics and interconnect delay times, (2) 3D can dramatically increase the number of interconnects and therefore increase the aggregate communication bandwidth between chips, and (3) 3D can allow dissimilar functions, technologies, and materials to be integrated. In the next part of this chapter we will talk about the 3D technology landscape and focus on IBM’s wafer-level integration research and development (R&D) efforts. We will describe layer transfer processing and wafer-level thinning, discuss bonding and interconnection processes, and show successful implementation of the

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10^-8 Omega-cm² for both n⁺ and p⁺ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.