Leathen Shi

Three-dimensional integrated circuits

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Single charge and confinement effects in nano‐crystal memories

Use of nano‐crystals of silicon in close proximity (1.5–4.5 nm) of a transistor channel lead to structures with pronounced memory where effects due to discrete number of electrons, confinement‐induced subbands in inversion layers and discrete energy states in quantum dots, random charge distribution in quantum dots, and transmission through a strong barrier are very important. Experimental results show plateaus in threshold voltage at low temperatures, spaced nearly equally apart, and indicative of single electron effects. Varying the oxide thickness shows strong influence on speed and charge retention. We confirm the strength of confinement effects and discuss the underlying considerations in the operation of the memory that are related to the reduced volume, strength of the barrier, and random distribution of the trapped charge in nano‐crystals.

High performance CMOS fabricated on hybrid substrate with different crystal orientations

A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

Hybrid-orientation technology (HOT): opportunities and challenges

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.

Extreme scaling with ultra-thin Si channel MOSFETs

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Wafer-level 3D integration technology

An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics

Epitaxial lift-off process enables the separation of III-V device layers from gallium arsenide substrates and has been extensively explored to avoid the high cost of III-V devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is confirmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin film transfer onto both rigid and flexible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, first built on thin active layers and then transferred to secondary substrates.