Annajirao Garimella

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-¿m CMOS process to supply 1.21 V to a load ranging from 1 ¿A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.

Frequency compensation techniques for op-amps and LDOs: A tutorial overview

Todays op-amp is not just a stand-alone IC, rather it is more custom and complex, catering the needs of highly integrated SoC. Tighter line and load regulation, low quiescent current operation, capacitor-free and wide-range output capacitor specifications are some of the contradicting requirements in an LDO, which drive newer topologies and newer frequency compensation techniques. The objective of this paper is to provide a tutorial treatment of some of the basics and recent advances in frequency compensation. Transistor level implementation of efficient LHP zero techniques and design examples are detailed.

Single Miller compensation using inverting current buffer for multi-stage amplifiers

A novel single Miller frequency compensation topology utilizing a current mirror as an inverting current buffer (SMCICB) for multi-stage amplifiers is proposed. An effective method for accurate placement of the Left-Half-Plane (LHP) zero, introduced by the current buffer is detailed. The SMCICB network effectively cancels the pole at output node, resulting in a single-pole system. This topology does not introduce additional transistors and static power dissipation. As a design example, we simulated a four-stage amplifier driving a 25kΩ//125-pF load, achieving 8.2MHz gain-bandwidth product, with 80μA of quiescent current and ±1.5Vpower supplies in a 0.5μm ON Semi 2P3M process CMOS. Simulation results, in good agreement with theoretical analysis, validate the proposed SMCICB scheme.

A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation

A new compensation technique known as tail compensation is applied to a two-stage CMOS operational amplifier. The compensation is established by a capacitor connected between the output node and the source node of the differential amplifier. For the selected opamp topology, tail compensation allows better performance in terms of bandwidth and power supply rejection ratio (PSRR) when compared to Miller and cascode compensation. Operational amplifiers using Miller, cascode and tail compensation were fabricated in a 0.5-μm 2P3M CMOS process. The circuits operate at a total quiescent current of 90 μA with ±1.5V power supplies. Experimental results show that tail compensation increases the unity-gain frequency by 60% and 25% and improves PSRR from the positive rail by 22 dB and 26 dB over a frequency range from 23 kHz to 3.0 MHz compared to Miller and cascode compensation, respectively.

Low-voltage, low-power rail-to-rail two stage op-amp with dynamic biasing and no Miller compensation

A novel compact low-voltage, low-power two-stage non-conventional op-amp with rail to rail input-output swing and without Miller compensation is introduced. The input stage uses floating gate transistors and a dynamic biasing scheme. Experimental results of a test chip are presented that validate the proposed circuit operating with a single supply as low as 1.4 V.

Pole-zero analysis of multi-stage amplifiers: A tutorial overview

Analyzing pole-zero locations of an amplifier is essential to 1) understand the characteristics of a circuit in the frequency domain, and 2) choose appropriate frequency compensation techniques to guarantee the stability of a circuit over a specified range of load resistance and capacitance. The objective of this paper is to provide tutorial treatment of the steps for analyzing poles and zeros in multi-stage amplifiers. These techniques can be equally applied for the analysis of power management circuits such as low-dropout voltage regulators (LDOs) and controllers for DC-DC converters.

Versatile multidecade CMOS voltage controlled oscillator with accurate amplitude and PWM control

A compact, versatile and very high speed approach for waveform generation is introduced. It generates triangle and square waveforms. The VCO has a very wide range of oscillating frequencies (from fractions of Hz to 100 MHz in 0.5 mum CMOS technology). The amplitude of the oscillations can be very precisely controlled. It can be used in frequency, amplitude, and pulse width modulation applications as well as in accurate piecewise linear waveform synthesis.

Low dropout (LDO) voltage regulator design using split-length compensation

We explore the application of split-length compensation to the design of a three-stage low dropout (LDO) voltage regulator. Initially, we review three basic compensation techniques, Miller, cascode, and split-length, and demonstrate their use in a multi-stage amplifier. It is found that stable designs are possible using single Miller compensation, whereas both cascode and split-length compensation require a Miller compensation network in parallel. Finally, we compare the three compensation techniques in terms of quiescent current, area, dropout voltage, unity-gain frequency, line and load transient response, and power supply rejection. For the LDO architecture selected, it is found that cascode and split-length compensation offer very similar performance, with the exception of quiescent current and area. Cascode compensation required 24% less total compensation capacitance, whereas split-length compensation used 14% less quiescent current.

Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview

Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.

Integrated CMOS Sensor Array for Optical Heterodyne Phase Sensing

A heterodyne interferometric CMOS 8 × 8 phase sensor array was developed to measure the spatial phase distribution of an optical wavefront. This sensor is suitable for measuring rapidly changing surface profiles and characterizing fast turbulence. Using an acousto-optic modulation frequency of 80 MHz and beat frequency of 10 kHz, the system calculates 8-bit phase data at each location in the array at a rate equal to the beat frequency. The phase computation is performed locally, digitized, and stored in 8-bit SRAM. Implemented in a 0.5-μm 2P3M CMOS process, the measured RMS phase error is 1.49° (1 LSB) and mismatch has σ = 4.76° (3.4 LSB). Experimental results, in agreement with theory, validate the proposed approach.