Paul M. Furth

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-¿m CMOS process to supply 1.21 V to a load ranging from 1 ¿A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.

A design framework for low power analog filter banks

We detail the design of multiresolution analog filter banks, linear models of cochlear function, with power dissipation being a prime engineering constraint. We propose that a reasonable goodness criterion is the information rate through the system, per watt of power dissipated. Speech applications requiring filter banks with a wide frequency tuning range, from 20 Hz to 20 kHz, and low power consumption make the transconductance-C integrator in subthreshold CMOS the preferable integrator structure. As an example, the dynamic range of a lowpass filter is computed and subsequently used to design a filter bank that models faithfully cochlear micro-mechanics. The power consumption of the entire filter bank is computed from analytical expressions and is estimated as 355 nW, at 68 kb/s overall information rate at the output of the system.

A 16-

A low-distortion three-stage class-AB audio amplifier is designed to drive a 16-Ω headphone speaker load. High power efficiency is achieved using fully differential internal stages with local common-mode feedback and replica biasing of the output stage. The threshold voltage of nMOS transistors was made comparable to that of pMOS transistors by negatively biasing the p-substrate in order to achieve high linearity. Multiple compensation networks guarantee the stability of the audio amplifier when driving a wide range of capacitive loads from 10 pF to 5 nF. Peak power delivered to the load is measured as 93.8 mW (corresponding to 46.9 mW RMS) with -77.9-dB total harmonic distortion; quiescent power is only 1.43 mW. The power-supply rejection ratio from both ±1.5-V supplies exceeds 63 dB over the entire audio frequency range. The design is implemented in a 0.5-μm CMOS process and occupies 0.34 mm2 of area.

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Todays op-amp is not just a stand-alone IC, rather it is more custom and complex, catering the needs of highly integrated SoC. Tighter line and load regulation, low quiescent current operation, capacitor-free and wide-range output capacitor specifications are some of the contradicting requirements in an LDO, which drive newer topologies and newer frequency compensation techniques. The objective of this paper is to provide a tutorial treatment of some of the basics and recent advances in frequency compensation. Transistor level implementation of efficient LHP zero techniques and design examples are detailed.

Audio Amplifier With 93.8-mW Peak Load Power and 1.43-mW Quiescent Power Consumption

The aim of this work is the efficient implementation of linear continuous-time cochlear models such as that proposed by Liu (1992, 1993). The basic filter element, a transconductance-C integrator with no linearization, is evaluated in terms of dynamic range and power consumption. Linearized transconductors which employ source degeneration via single and multiple diffusers yield no net increase in current noise density, whereas linear range is improved eight and four times, respectively. Experimental results verify this improvement.

Frequency compensation techniques for op-amps and LDOs: A tutorial overview

We convert a low-voltage low-transistor-count wide-swing multistage pseudoclass-AB amplifier proposed by Mita et al. to a true-class-AB amplifier. The conversion is made possible using gate-drain feedback to combine two inverting common- source amplifiers to form a single noninverting stage. Both the pseudoclassand true-class-AB amplifiers were fabricated in a 0.5-μm CMOS 2P3M process. They are designed to operate from ±1.25-V supplies at a nominal quiescent current of 175 μA and a minimum phase margin of 45° when driving capacitive loads from 1 to 200 pF and resistive loads from 500 Ω to 1 MΩ. The total com- pensation capacitance of the proposed class-AB amplifier is 12 pF, which is 50% less than the pseudoclass-AB amplifier. The simu- lated unity-gain frequency of the class-AB amplifier is 4.9 MHz at a load of 25 pF||1kΩ, which is 88% higher than that of the pseudoclass-AB amplifier. Experimental measurements show that the proposed amplifier has a maximum total bias current of 175 μA, as compared with 1.05 mA for the pseudoclass-AB am- plifier. Measured slew rates of the proposed amplifier are 2.7 and 3.3 V/μs, twice as much as those of its pseudoclass-AB counterpart.

Cochlear models implemented with linearized transconductors

A novel single Miller frequency compensation topology utilizing a current mirror as an inverting current buffer (SMCICB) for multi-stage amplifiers is proposed. An effective method for accurate placement of the Left-Half-Plane (LHP) zero, introduced by the current buffer is detailed. The SMCICB network effectively cancels the pole at output node, resulting in a single-pole system. This topology does not introduce additional transistors and static power dissipation. As a design example, we simulated a four-stage amplifier driving a 25kΩ//125-pF load, achieving 8.2MHz gain-bandwidth product, with 80μA of quiescent current and ±1.5Vpower supplies in a 0.5μm ON Semi 2P3M process CMOS. Simulation results, in good agreement with theoretical analysis, validate the proposed SMCICB scheme.

Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier

We compare designs of low-power CMOS comparators with programmable hysteresis. We chose two baseline comparators: a two-stage CMOS op-amp with output inverter and a folded-cascode op-amp with output inverter. To these baseline circuits, we add programmable hysteresis using two methods. The first method uses positive feedback to unbalance the input differential pair. The second method uses positive feedback to steer current through a fixed-value resistor. The comparators were implemented in a 0.5µm CMOS process and operate with ±1.25V supplies. For an input voltage that is 10mV beyond the switching point, the propagation delays of the two-stage comparator with programmable hysteresis are measured as 932ns for the first method biased at 3.1µA and 672ns for the second method biased at 4µA.

Single Miller compensation using inverting current buffer for multi-stage amplifiers

A new compensation technique known as tail compensation is applied to a two-stage CMOS operational amplifier. The compensation is established by a capacitor connected between the output node and the source node of the differential amplifier. For the selected opamp topology, tail compensation allows better performance in terms of bandwidth and power supply rejection ratio (PSRR) when compared to Miller and cascode compensation. Operational amplifiers using Miller, cascode and tail compensation were fabricated in a 0.5-μm 2P3M CMOS process. The circuits operate at a total quiescent current of 90 μA with ±1.5V power supplies. Experimental results show that tail compensation increases the unity-gain frequency by 60% and 25% and improves PSRR from the positive rail by 22 dB and 26 dB over a frequency range from 23 kHz to 3.0 MHz compared to Miller and cascode compensation, respectively.

On the design of low-power CMOS comparators with programmable hysteresis

This paper provides a direct comparison between a fast binary counter, built using a hierarchical Manchester carry chain, and a counter built using a linear feedback shift register (LFSR). The comparison is focused on speed, power and area consumption. We demonstrate the use of LFSRs as an alternative to conventional binary event counters. In order to use an LFSR as a counter, we developed an efficient algorithm for decoding the pseudo-random bit patterns of the LFSR counter to a known binary count. We implement 4-bit, 8-bit, 16-bit and 32-bit LFSR and binary counters in a 0.5-µm CMOS process. The hypotheses that LFSR counters leads to reduced area and higher speed were validated using simulation and measurement results.