Punith R. Surkanti

Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier

We convert a low-voltage low-transistor-count wide-swing multistage pseudoclass-AB amplifier proposed by Mita et al. to a true-class-AB amplifier. The conversion is made possible using gate-drain feedback to combine two inverting common- source amplifiers to form a single noninverting stage. Both the pseudoclassand true-class-AB amplifiers were fabricated in a 0.5-μm CMOS 2P3M process. They are designed to operate from ±1.25-V supplies at a nominal quiescent current of 175 μA and a minimum phase margin of 45° when driving capacitive loads from 1 to 200 pF and resistive loads from 500 Ω to 1 MΩ. The total com- pensation capacitance of the proposed class-AB amplifier is 12 pF, which is 50% less than the pseudoclass-AB amplifier. The simu- lated unity-gain frequency of the class-AB amplifier is 4.9 MHz at a load of 25 pF||1kΩ, which is 88% higher than that of the pseudoclass-AB amplifier. Experimental measurements show that the proposed amplifier has a maximum total bias current of 175 μA, as compared with 1.05 mA for the pseudoclass-AB am- plifier. Measured slew rates of the proposed amplifier are 2.7 and 3.3 V/μs, twice as much as those of its pseudoclass-AB counterpart.

Pole-zero analysis of multi-stage amplifiers: A tutorial overview

Analyzing pole-zero locations of an amplifier is essential to 1) understand the characteristics of a circuit in the frequency domain, and 2) choose appropriate frequency compensation techniques to guarantee the stability of a circuit over a specified range of load resistance and capacitance. The objective of this paper is to provide tutorial treatment of the steps for analyzing poles and zeros in multi-stage amplifiers. These techniques can be equally applied for the analysis of power management circuits such as low-dropout voltage regulators (LDOs) and controllers for DC-DC converters.

Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview

Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.

Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp

In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented in a 180-nm CMOS process with a power supply of 1.8V while operating with a quiescent current of 110μA. Results indicate that the proposed voltage buffer compensation using FVF improves the Unity Gain Frequency from 5.5MHz to 12.2MHz compared to Miller compensation. Also, the proposed technique enhances the transient response while lowering the compensation capacitance by 47% and 17.7% compared to Miller and common-drain compensation topologies. Utilization of FVF or its variants as a voltage buffer in a feedback compensation network has wide potential applications in the analog design space.

A high precision and high speed voltage-mode loser/winner-take-all circuit

This paper presents a voltage-mode loser/winner-take-all circuit that has high speed and accuracy with low power consumption and which is suitable for LED driver applications. The implementation mixes analog and digital circuits in order to help in improving precision. The design is based on a hysteretic comparator and, as such, achieves a very fast response time. The circuit is implemented in the IBM-180 nm process and operates with a supply of 1.8 V and 20 μA current. Simulated results show that the circuit can detect differences as low as 3 mV between multiple inputs with almost no offset and maximum of 1.5 mV offset if the input difference is less than 3 mV. The simulated delay of the circuit is less than 10 ns during an input transition.

High-efficiency, high-dimming ratio LED driver

A high-efficiency, high-dimming ratio LED driver, capable of driving two standard white LEDs in series, is presented in this paper. A synchronous boost converter with on-chip switches and PWM controller is used as the LED driver. The LED current is sensed using voltage-mode feedback to maintain a constant load current. The output sense resistor in a conventional LED driver is replaced by the disconnect switch with an equivalent on-resistance to increase efficiency. Lossless current-mode feedback, in which the inductor current is sensed via the on-resistance of the boost series switch, is used to improve stability. Dimming control logic is implemented with a 10-bit counter and a 10-to-1 MUX, generating 10 dimming ratios ranging from 2:1 at a frequency of 625 kHz to 1024:1 at 610 Hz. The simulated efficiency of the LED driver alone is 86.1% and that of the LED driver with dimming control is 85.4%.

A high-speed image centroid computation sensor

We present a fully-integrated analog CMOS image centroid computation sensor. A 40×40 pixel array is designed and fabricated in a 0.5-μm CMOS process. The proposed centroid computation circuit achieves 7 times improvement in bandwidth compared to similar circuits in the literature. Moreover, the incorporation of a linearized transconductor improves precision in the computed centroid. The sensor is designed to operate over a wide range of photocurrents from 10 pA to 1 μA. Test results of the proposed architecture verify its superior performance.

Bias-line compensation in multi-stage amplifiers

In this paper, a novel bias-line compensation (BLC) using inverting current buffer for multi-stage amplifiers is proposed. This technique uses a compensation capacitor connected between the output node and low-impedance bias line, which helps in increasing the bandwidth and improving PSRR. The proposed technique is implemented in a widely-adopted low-voltage, high-gain and wide-swing pseudo-class AB amplifier [1]. The amplifier is conventionally compensated with reverse-nested Miller compensation. The results show that bias-line compensation improves the bandwidth by 50% and PSRR by 5dB with ±1.25V power supplies. The amplifier with bias-line compensation is stable for a capacitive load in the range of 1pF to 200pF. The chip was fabricated in a 0.5µm 2P3M process. Measurement results validate the effectiveness of the proposed method.

High bandwidth class-AB amphfier with high slew rate and fast current sensing for envelope tracking applications

This work presents the design of a high-bandwidth and high slew rate class-AB amplifier in a linear assisted hybrid converter for envelope tracking (ET) applications. ET has become prevalent for improving the efficiency of RF power amplifiers (PA) in portable devices when transmitting LTE signals. The class-AB amplifier in the hybrid converter provides the AC power to the PA, whereas the DC power is provided by a DC-DC converter. The class-AB amplifier is designed to track the LTE signal envelope, up to 20 MHz in bandwidth. Optimization is required to improve the efficiency of the system. A novel high-speed current-sense block is implemented to accurately sense the output stage currents of the class-AB amplifier. The amplifier is implemented in a 0.5–μ\Ά CMOS process, operates from a 3.6–5.0 V supply and is capable of driving a resistive load range from 20–4 Ω. The class-AB amplifier achieves 80 MHz UGF at a 4 Ω load, consuming roughly 33 mA quiescent current. Simulation results shows the tracking of 20 MHz LTE signals with an RMS error better than −34 dB.

On the analysis of low output impedance characteristic of flipped voltage follower (FVF) and FVF LDOs

The flipped voltage follower (FVF), a variant of the common-drain transistor amplifier, comprising local feedback, finds application in circuits such as voltage buffers, current mirrors, class AB amplifiers, frequency compensation circuits and low dropout voltage regulators (LDOs). One of the most important characteristics of the FVF, is its low output impedance. In this tutorial-flavored paper, we perform a theoretical analysis of the transfer function, poles and zeros of the output impedance of the FVF and correlate it with transistor-level simulation results. Utilization of the FVF and its variants has wide application in the analog, mixed-signal and power management circuit design space.