Anne-Marie Goethals

Lithography Options for the 32 nm Half Pitch Node and Beyond

Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 nm immersion lithography with high index materials, enabling NA > 1.6; 193 nm double patterning and EUV lithography. In this paper the evolution of these three options over 2008 is discussed. The extendibility of these options beyond 32 nm half pitch is important for the final choices to be made. During 2008, the work on high index 193 nm immersion lithography has been stopped due to lack of progress in high index optical material and high index liquid development. Double patterning has made a lot of progress but cost concerns still exist. Preferred are those resists which support pattern or image freezing techniques in order to step away from the complex litho-etch-litho-etch approach and make double patterning more cost effective. For EUV, besides the high power light source, the resist materials need to meet very aggressive sensitivity specifications and need to maintain simultaneously performance in terms of resolution and line width roughness. Furthermore, EUV reticles encounter serious challenges, primarily related to mask defectivity.

Resist surface investigations for reduction of Line-Edge-Roughness in Top Surface Imaging technology

The Line-Edge-Roughness (LER) of resist pattern on fine feature has been characterised by means of top/down line width measurements by SEM in Top Surface Imaging (TSI) technology. The resist surface investigation using AFM has provided a correlation between resist Surface Roughness (SR) and the formation mechanism of LER. LER has been improved to 7 nm at 0.18 @mm dense patterns by the optimisation of dry development conditions based on these resist surface investigation.

Full-field EUV and immersion lithography integration in 0.186μm 2 FinFET 6T-SRAM cell

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

Sub-quarter micron phase shifting lithography using the desire process at 248 nm (deep UV)

Abstract The lithographic performance of phase shifting and transmission masks are compared. This paper describes the ultimate resolution and process latitudes, that can be obtained by combining a phase shift mask with the DESIRE process at 248 nm. Special emphasis is put on the influence of coherence. Both simulation and experimental results are given.

Applicability of dry developable deep-UV lithography to sub-0.5 um processing

Dry developable lithography as represented by the DESIRE process, is one of the most attractive surface imaging technologies for advanced optical lithography. A resolution of 0.25 micrometers has been demonstrated with this process, using i-line exposure in conjunction with a phase shifting mask and by deep-UV exposure (248 nm). Surface imaging is especially suited for deep-UV lithography since it overcomes the poor CD-control over topography encountered with highly transparent wet developable resists. In this work the applicability of DESIRE to sub-0.5 micrometers processing has been studied. With regard to the silylation process, crosslinking effects resulting from the radiation at 248 nm have been found to reduce the Si incorporation. This crosslinking effect can be reduced by the use of alternative silylating agents (such as TMDS 1,1,3,3-tetramethyl disilazane), which silylate at a lower temperature. A comparison of processing latitudes for lines and for contact holes has been made for silylation with HMDS and with TMDS. Other issues related to the implementation of DESIRE in typical CMOS processing, such as dry etch compatibility and resist stripping have also been addressed.

Lithography for sub-90nm applications

In order to cope with the progressive scaling of CMOS, new lithography techniques are introduced for sub-90nm applications. Among them are the introduction of the 157nm wavelength and extreme ultra-violet lithography (EUVL). However, the delay in availability of these tools requires the extension of 193nm lithography towards future technology nodes. This paper gives an overview of the latest breakthroughs and the remaining challenges to the lithography community.

Evaluation of methods to reduce linewidth variation due to topography for i-line and deep-UV lithography

For deep submicron lithography, reduction of linewidth variation due to topography is critical. While advanced resists are available which demonstrate wide process latitude on flat substrates, their performance on realistic topography is not adequate. A new method of predicting performance over topography using data taken from flat substrates is described. The method uses data from both maximum and minimum incoupling resist thicknesses to determine the overlapping depth of focus (ODOF). The usefulness of the ODOF approach in predicting process latitude for substrates with topography is shown.nResults for both I-line and deep UV imaging on poly gate level topography are presented. Results obtained with 2 top anti-reflection (TAR) layers (Hoechst Aquatar and a non-commercial TAR material) are compared to those from a dyed resist, an anti-reflection coating (ARC) and a contrast enhancement material (CEM). Methods of determining the optimal TAR thickness experimentally are presented. TAR materials give the best results for I-line.

JESSI Project E 162: status of the deep-UV resist

Within the joint European project `JESSI E 162 we pursue deep UV image processing for 0.35 micrometers lithography in chip production. To reach this goal, major advancements have to be made in three areas: stepper, resist, and track. In this paper, the status of the JESSI positive deep UV resist is presented. Based on the SUCCESS resist concept a stable resist process was developed. The major achievements are: linewidth stability for 0.35 micrometers lines and larger ones during delay times up to 120 min between exposure and PEB, 0.24 micrometers lines stable for 30 min, linearity down to 0.35 micrometers (NA 0.42), resolution of 0.22 micrometers with phase-shift mask (NA 0.42), and dry etch resistance better than conventional novolac resists.

DUV lithography for 0.35 µm CMOS processing

The performance of positive and negative tone resists on the critical levels of a 0.35 @mm CMOS process has been evaluated. The use of a darkfield reticle suppresses reflections in lens and resist. Therefore reflection problems are reduced for poly gate patterning with a negative tone resist. If a positive resist is used it should be combined with a bottom ARC. For the contact hole level a positive tone resist is required. Good performance, including batch uniformity is obtained for 0.5 @mm holes. For 0.4 @mm contact holes, latitudes needed to be improved and this has been realised by either the combination of mask biasing and focus drilling or the use of an attenuated phase shifting reticle. For metal patterning, again positive and negative resists have been studied. An important issue here is the interaction between the acid formed upon exposure and the underlying TiN layer.

Stability of silylated images for application to dry developable deep-UV lithography

Abstract Delay time effects and pattern distortion are limiting factors for the performance of the DESIRE process in DUV, under certain experimental conditions. These problems were found to be related to the stability of the silylated image. Optimization of processing conditions, modification of the resist composition and selection of the appropriate silylating agent resulted in a reliable and stable process with excellent resolution and latitude.