Kurt G. Ronse

Comparison of various phase-shift strategies and application to 0.35-μm ASIC designs

Phase shifting masks for real circuits have been investigated extensively only for DRAMs. In this paper, we report on the applicability of i-line phase shifting lithography to the production of application specific ICs (ASICs). The performance of several phase shift strategies is compared, using an i-line stepper with a numerical aperture of 0.48. Data preparation and mask technology considerations are taken into account. Emphasis is placed on the two most critical levels: poly gate and contact window. Results on poly topography are shown. For the poly level, the frequency doubling alternating shifter strategy in combination with a positive resist seems to be capable of printing features down to 0.35 micrometers CD, but the development of automatic phase shift level generation software is still in a preliminary phase. Edge contrast enhancement strategies in combination with a negative resist are considerably simpler, in particular the halftone PSM strategy. These strategies are also very useful in combination with a positive resist for the contact level, where a doubling of the process latitudes was obtained.

Characterization and correction of optical proximity effects in deep‐ultraviolet lithography using behavior modeling

We present the characterization of optical proximity effects and their correction in deep‐UV lithography using an empirically derived model for calculating feature sizes in resist. The model is based on convolution of the mask pattern with a set of kernels determined from measuring the printed test structures in resist. The fit of the model to the measurement data is reviewed. The model is then used for proximity correction using commercially available proximity correction software. Corrections based on this model is effective in restoring resist linearity and in reducing line‐end shortening. It is also more effective in reducing optical proximity effects than corrections based only on aerial image calculations.

Thin film interference effects in phase shifting masks causing phase and transmittance errors

Phase shifting masks have proven their potential to enhance resolution and depth‐of‐focus in optical lithography. Nevertheless, many questions still have to be solved, before the phase shifting concept can be introduced in production lines. Controllable mask fabrication is a major concern. This article addresses the influence of physical material properties and process steps in the attempt to fabricate phase shifting masks with acceptable phase shift and transmittance. Spectrophotometer measurements and computer simulations showed the need of matched refractive indices for all transparent materials in the reticle. Second, the sensitivity of the lithographic performance to these shifter deviations was investigated by aerial image simulations. These predicted a high sensitivity to phase errors, especially for negative resists. Using a negative tone top surface imaging resist process and a positive tone wet developed resist, experiments confirmed these predictions. Special attention was paid in finding an ac...

Metrology method for the correlation of line edge roughness for different resists before and after etch

This paper proposes a methodology method to measure line edge roughness (LER) using scanning electron microscopy (SEM) with LER and critical dimension (CD) variation software both for resist lines as well as for silicon lines. The method is based on the spatial frequency of the LER which means that the high- and low-frequency behaviour of LER can be evaluated. As an application, different resists after litho and after polysilicon etch were compared.

Influence of gate patterning on line edge roughness

It is shown by simulation that the line edge roughness (LER) on the gates causes fluctuations on transistor performance [J. A. Croon et al., “Line edge roughness: Characterization, modeling, and impact on device behavior,” Proceedings of the IEDM, 2002; “Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield” (to be published)]. Efforts are underway to investigate the influence on device performance experimentally. In this article, the transfer of the LER of the resist pattern into the poly silicon layer is investigated. For the experimental setup isolated gate lines ranging between 50–180 nm were patterned with an e-beam lithography. The resist line patterns are generated with some additional programmed LER. After the e-beam lithography step the processing was continued with etching the poly-Si, resist strip, and SiON removal. Using an offline software analysis tool for the edge detection based on SEM pictures, it was possible to determine the influence of process...

Lithography Options for the 32 nm Half Pitch Node and Beyond

Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 nm immersion lithography with high index materials, enabling NA > 1.6; 193 nm double patterning and EUV lithography. In this paper the evolution of these three options over 2008 is discussed. The extendibility of these options beyond 32 nm half pitch is important for the final choices to be made. During 2008, the work on high index 193 nm immersion lithography has been stopped due to lack of progress in high index optical material and high index liquid development. Double patterning has made a lot of progress but cost concerns still exist. Preferred are those resists which support pattern or image freezing techniques in order to step away from the complex litho-etch-litho-etch approach and make double patterning more cost effective. For EUV, besides the high power light source, the resist materials need to meet very aggressive sensitivity specifications and need to maintain simultaneously performance in terms of resolution and line width roughness. Furthermore, EUV reticles encounter serious challenges, primarily related to mask defectivity.

High yield sub-0.1µm 2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Opportunities and challenges in device scaling by the introduction of EUV lithography

EUV lithography is generally considered as the technology to take over from 193nm immersion lithography, but has been delayed due to a number of critical problems that remain to be solved. The purpose of this paper is to illustrate the improvements in process complexity, reduced design restrictions and reduced processing costs in case EUVL would be available for the 14nm logic node and beyond. We have shown that the readiness of EUVL is critical to keep scaling the logic devices following the pace of Moores law, continuing the performance improvements of the devices at an acceptable processing cost and cycle time, still allowing sufficient freedom to the system designers in terms of design restrictions.

Resist surface investigations for reduction of Line-Edge-Roughness in Top Surface Imaging technology

The Line-Edge-Roughness (LER) of resist pattern on fine feature has been characterised by means of top/down line width measurements by SEM in Top Surface Imaging (TSI) technology. The resist surface investigation using AFM has provided a correlation between resist Surface Roughness (SR) and the formation mechanism of LER. LER has been improved to 7 nm at 0.18 @mm dense patterns by the optimisation of dry development conditions based on these resist surface investigation.

Optical lithography techniques for 0.25 /spl mu/m and below: CD control issues

It is generally accepted that optical lithography will be the technology of choice for the fabrication of devices for several generations to come. In this paper some of the current challenges to print 0.25 /spl mu/m dimensions are addressed. Although the mainstream technologies for 0.35 /spl mu/m and 0.25 /spl mu/m processes are more or less settled, the main challenge will most likely be CD control. Optical proximity effects and CD variations resulting from substrate reflections start to play a major role in the CD budget. Several methods to reduce these contributions (such as the use of optical proximity correction techniques and the use of anti-reflection coatings and surface imaging processes) are presented. Moreover, it will be indicated that considerable improvements in CD control can be obtained by optimization of stepper parameters. Finally, in an attempt to indicate the future of optical lithography, a simulation study is presented, indicating the available process latitudes which can be obtained by combining several of the above listed techniques.