Antara Ain

Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models

Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog simulation. In this article we present an approach for automatic generation of behavioral models for PMU components from top-down skeleton models, fitted with parameter values estimated by bottom-up parameter extraction algorithms. It is shown that replacing PMU components with these autogenerated hybrid automata-based abstract behavioral models enables significant simulation speedup (> 20X on our industrial test cases) and helps in early detection of integration errors. The article also justifies the level of accuracy in our models with respect to the goal of verifying integrated PMUs. The approach presented in this work is implemented in the form of a tool suite called Chassis.

Feature Indented Assertions for Analog and Mixed-Signal Validation

The acceptance criteria for analog designs are traditionally defined in terms of real-valued features defined over behavioral responses. For example, rise time, peak overshoot, and settling time are features of the response of a second-order system under a step input. Designers of analog and mixed-signal (AMS) designs typically like to see whether the relevant features lie within their specified ranges, and if so, by what margin. Assertions are capable of capturing the acceptance criteria, but they do not help in evaluating how well (or by what margin) the design satisfies the specification. We introduce the notion of Feature Indented Assertions (FIAs) for overlaying the definition of real-valued features over the syntactic fabric of AMS assertions. In this paper, we present the formal syntax and semantics of our language, FIA, and demonstrate its ability to capture a wide variety of AMS features. We present our dynamic feature evaluation tool that plugs into standard AMS simulators through Verilog Procedural Interfaces and evaluates features over simulation. At the heart of this tool, we have our interval arithmetic-based algorithm for monitoring features over continuous time and value domains. This algorithm is presented with corresponding proofs of correctness and with results over industrial testcases.

A formal approach for specification-driven AMS behavioral model generation

Behavioral models for analog and mixed signal (AMS) designs are developed at various levels of abstraction, using various types of languages, to cater to a wide variety of requirements, ranging from verification, design space exploration, test generation, and application demonstration. In this paper we present a high-level formalism for capturing the AMS design intent from the specification and present techniques for automatic generation of AMS behavioral models. The proposed formalism is a language independent one, yet the design intent is modeled at a level of abstraction which enables easy translation into common modeling standards. We demonstrate the translation into VerilogA and SPICE, which are fundamentally different standards for behavioral modeling. The proposed approach is demonstrated using a family of Low Dropout Regulators (LDO) as the reference.

Monitoring AMS Simulation: From Assertions to Features

The complexity of analog mixed-signal (AMS) designs motivates the designers to analyze these systems in terms of features, which can be defined as the characterizing behavioral attributes of the designs. The first step towards automating the evaluation of feature values is to express the feature definitions in a formal way, and then to evaluate them over behavioral signatures. In this paper we present a framework for evaluating feature values over standard simulation platforms. Case studies over several circuit families are presented to illustrate the proposed methodology.

A Framework for Automated Feature Based Mixed-Signal Equivalence Checking.

The presence of real valued variables that change continuously over dense real time makes it unrealistic to lift the definitions of equivalence used in the digital domain to the analog/mixed-signal domains. Thus the notion of equivalence between infinite state systems such as analog and mixed signal (AMS) circuits have been traditionally expressed in terms of its domain specific features or behavioral signatures. This paper formalizes the definition of feature based equivalence and presents a framework for monitoring feature based equivalence using a simulation based approach. The proposed methodology has been illustrated using various AMS circuit families.

Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs

Automated monitoring of power grids has become an important requirement in view of the complexity of such systems. Assertions are formal properties which define the admissible behaviors of the system and can be defined as the characterizing behavioral attributes under specific scenarios of the system. Though observability of the grid has increased with Phasor Measurement Units (PMUs), diagnosing the occurrence of various events in a grid is still not obvious from the data set of the PMUs and hence may require synchronous monitoring and analysis of a number of PMUs. In this work, we present an approach for localizing and classifying a transmission line fault in a grid using assertions defined over behaviors caused by that fault. The first step towards automating this task is to express the inadmissible behaviors in a formal way, and then to evaluate them over time-stamped data obtained from the PMUs of the grid. The outcome of the assertions obtained is finally used to localize and classify the transmission line fault that has occurred in the grid. The proposed methodology has been demonstrated on PMU data of the Indian power grid.

Post-silicon debugging of PMU integration errors using behavioral models

Power Management Units (PMUs) are large integrated mixed-signal circuits, having several linear and switching regulators for supplying customized voltages to the components of a low power platform. The presence of analog components in the integration circuitry makes it very hard to eliminate all pre-silicon integration errors, including some common types of errors. During post-silicon debug the designer typically wants to rule out the common types of errors before considering other types of bugs. This is facilitated by a mechanism for mapping back from observed anomalies to these known types of integration errors. We present an approach that enables this task by creating a fault map through pre-silicon analysis of the PMU. The proposed pre-silicon analysis makes use of formal properties and behavioral models to accelerate simulation, and is thereby able to create the fault map within feasible limits of time. We present experimental results on industrial strength PMUs to demonstrate the feasibility of this step. We also present a post-silicon debugging approach, which uses the inverse of the fault map to shortlist the set of known types of integration errors that must be ruled out before looking for other forms of bugs.

Auto-generation of ams behavioral models in different languages from hybrid automata

This paper proposes a methodology for automatic generation of behavioral models of analog and mixed signal circuits in different languages from hybrid system based specification. The proposed approach captures the design specification of a class of circuits into a language independent high level library of models. Taking the user input, and the domain knowledge from the specification, and by parsing the library of models, the model generator automatically generates the behavioral models in different languages. In this work, the behavioral models are developed in Verilog-A and SPICE languages, which are often used in industrial applications and are also structurally different. The methodology is explained with a synthetic example of programmable gain amplifier with automatic gain control circuit.

A study of modeling techniques in use in digital and mixed-signal domains for semi-formal verification

Simulation-based techniques are the defacto standard for the verification of industrial designs. Since verification effort takes about 70% of the time of the design phase, it is important to expedite the simulation process in order to reduce the overall verification effort. Modeling-based techniques play an important role towards achieving the speed-up by expediting many subtasks of the overall verification process. In this paper we present a study of the different modeling techniques that are primarily used for semi-formal verification of modern-day industrial digital and mixed-signal designs and the efficacy of the same for achieving the verification speed-up.