Subhankar Mukherjee
Indian Institute of Technology Kharagpur
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Publication
Featured researches published by Subhankar Mukherjee.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2011
Subhankar Mukherjee; Pallab Dasgupta; Siddhartha Mukhopadhyay
As research on developing assertion languages for the analog and mixed-signal (AMS) domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like property specification language and SystemVerilog assertions into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper, we show that by using auxiliary forms of formal specifications such as abstract state machines and real-valued functions, called auxiliary functions, as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. In addition, we present complexity results for the satisfiability problem of such specifications. This approach leverages the growing adoption of AMS behavioral modeling in the industry. This paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
international conference on vlsi design | 2013
Rajdeep Mukherjee; Pallab Dasgupta; Ajit Pal; Subhankar Mukherjee
Complex low power integrated circuits use global power management strategies to orchestrate the switching between power states of multiple power domains. One of the primary challenges in verifying such power management architectures stems from the mixed implementation of such strategies, where the local power controllers are in hardware and the global power management is implemented in software/firmware. In this paper we present an approach for using formal methods for verifying such hardware / software power management implementations. To the best of our knowledge, this is the first approach for formal verification of such implementations.
ACM Transactions on Design Automation of Electronic Systems | 2012
Subhankar Mukherjee; Pallab Dasgupta; Siddhartha Mukhopadhyay; Scott Little; John Havlicek; Srikanth Chandrasekaran
The verification community anticipates the adoption of assertions in the Analog and Mixed-Signal (AMS) domain in the near future. Several questions need to be answered before AMS assertions are brought into practice, such as: (a) How will the languages for AMS assertions be different from the ones in the digital domain? (b) Does the analog simulator have to be assertion aware? (c) If so, then how and where on the time line will the AMS assertion checker synchronize with the analog simulator? and (d) What will be the performance penalty for monitoring AMS assertions accurately over analog simulation? This article attempts to answer these questions through theoretical analysis and empirical results obtained from industrial test cases. We study logics which extend Linear Temporal Logic (LTL) with predicates over real variables, and show that further extensions allowing the binding of real-valued variables across time makes the logic undecidable. We present a toolkit which can integrate with existing AMS simulators for checking AMS assertions on practical designs. We study the problem of synchronizing the AMS simulator with the AMS assertion checker and demonstrate the performance penalty of different synchronization options.
international conference on vlsi design | 2011
Subhankar Mukherjee; Pallab Dasgupta
As research on developing assertion languages for the AMS domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like PSL and SVA into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper we show that by using auxiliary forms of formal specifications such as abstract state machines and real valued functions as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. This approach leverages the growing adoption of AMS behavioral modeling in the industry. The paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
bioinformatics and biomedicine | 2014
Rama Srikanth Mallavarapu; Tae-jin Ahn; Subhankar Mukherjee; Ajit S. Bopardikar; Garima Agarwal; Taesung Park
It is known that the gene level aberrations for a given cancer could vary across patients. As a result, a single therapy may not be suitable for every patient. However, these genetic aberrations may occur in similar pathways across patients. Therefore a study at pathway/subnetwork is more effective than at gene level. In this paper, we propose a method at this level to classify pathways (sub-networks) as functionally coupled and functionally independent. For this, we propose novel interaction measures. We show how these can be used to link and classify subnetworks using breast cancer as an example. Such methods will play an important role in patient stratification in order to develop personalized treatment options.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2012
Subhankar Mukherjee; Pallab Dasgupta
There has been considerable focus recently on research on developing assertion checking capability with analog and mixed-signal (AMS) simulators. Such tools must be able to detect failures of assertions in simulation traces and report the windows in which failures have been detected. Due to the dense real time semantics of AMS assertions, the task of identifying the minimal debugging window for each failure is not a trivial problem. This paper addresses the problem of computing the minimal debugging window in failure traces for AMS assertions and presents an algorithm which is linear in regards to the size of the assertion and the size of the trace.
design, automation, and test in europe | 2009
Subhankar Mukherjee; Antara Ain; S. K. Panda; Rajdeep Mukhopadhyay; Pallab Dasgupta
Behavioral models for analog and mixed signal (AMS) designs are developed at various levels of abstraction, using various types of languages, to cater to a wide variety of requirements, ranging from verification, design space exploration, test generation, and application demonstration. In this paper we present a high-level formalism for capturing the AMS design intent from the specification and present techniques for automatic generation of AMS behavioral models. The proposed formalism is a language independent one, yet the design intent is modeled at a level of abstraction which enables easy translation into common modeling standards. We demonstrate the translation into VerilogA and SPICE, which are fundamentally different standards for behavioral modeling. The proposed approach is demonstrated using a family of Low Dropout Regulators (LDO) as the reference.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2012
Subhankar Mukherjee; Pallab Dasgupta
Sampling has been one of the key issues in simulation-based verification of analog and mixed signal (AMS) systems. Recent attempts toward extending assertion languages to the AMS domain has brought forward an obvious question. In what way should sampling be done to ensure that assertions are evaluated correctly? Increasing sampling granularity often comes with substantial simulation time overhead. On the other hand, interpolation of the analog signals between consecutive samples introduces inaccuracies in the signal values and, hence, in the truth of the assertions. This paper explores how temporal assertions are handled for inadequately sampled signals. We propose a three-valued semantics (true, false, and unknown) for AMS assertions to address the uncertainty caused by the inadequacy of samples. The evaluation algorithm reports the time intervals where additional samples are required to resolve the uncertainty, thereby paving the way for adaptive sampling refinement in assertion aware AMS simulation.
data mining in bioinformatics | 2016
Rama Srikanth Mallavarapu; Tae Jin Ahn; Subhankar Mukherjee; Ajit S. Bopardikar; Garima Agarwal; Taesung Park
Cancer is a heterogeneous disease in that a single therapy may not be suitable for every patient. This is because, even within a single cancer, gene-level aberrations vary across patients. However, when genes are viewed at sub-network level, it is observed that these aberrations occur in sub-networks that are conserved across patients. Investigation of cancer gene sub-networks is therefore expected to yield greater insights. Also, multiple sub-networks could be involved in propagation of cancer and therefore coupling between them is of great importance. We present a method to measure and quantify coupling between two given sub-networks. For this we present interaction measures based on connecting genes and common neighbourhoods between sub-networks. We demonstrate this method using breast cancer focused around MET pathway and discuss functional coupling of various associated sub-networks. Studies based on such methods will play an important role in patient stratification and development of effective targeted therapies.
Integration | 2013
Antara Ain; Subhankar Mukherjee; Pallab Dasgupta; Siddhartha Mukhopadhyay
Power Management Units (PMUs) are large integrated mixed-signal circuits, having several linear and switching regulators for supplying customized voltages to the components of a low power platform. The presence of analog components in the integration circuitry makes it very hard to eliminate all pre-silicon integration errors, including some common types of errors. During post-silicon debug the designer typically wants to rule out the common types of errors before considering other types of bugs. This is facilitated by a mechanism for mapping back from observed anomalies to these known types of integration errors. We present an approach that enables this task by creating a fault map through pre-silicon analysis of the PMU. The proposed pre-silicon analysis makes use of formal properties and behavioral models to accelerate simulation, and is thereby able to create the fault map within feasible limits of time. We present experimental results on industrial strength PMUs to demonstrate the feasibility of this step. We also present a post-silicon debugging approach, which uses the inverse of the fault map to shortlist the set of known types of integration errors that must be ruled out before looking for other forms of bugs.