Priyankar Ghosh

Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications

We present formal methods for determining whether a set of components with given reliability certificates for specific functional properties are adequate to guarantee desired end-to-end properties with specified reliability requirements. We introduce a formal notion for the reliability gap in component-based designs and demonstrate the proposed approach for analyzing this gap using a case study developed around an Elevator Control System.

Algorithms for generating ordered solutions for explicit and/or structures

We present algorithms for generating alternative solutions for explicit acyclic AND/OR structures in non-decreasing order of cost. The proposed algorithms use a best first search technique and report the solutions using an implicit representation ordered by cost. In this paper, we present two versions of the search algorithm - (a) an initial version of the best first search algorithm, ASG, which may present one solution more than once while generating the ordered solutions, and (b) another version, LASG, which avoids the construction of the duplicate solutions. The actual solutions can be reconstructed quickly from the implicit compact representation used. We have applied the methods on a few test domains, some of them are synthetic while the others are based on well known problems including the search space of the 5-peg Tower of Hanoi problem, the matrix-chain multiplication problem and the problem of finding secondary structure of RNA. Experimental results show the efficacy of the proposed algorithms over the existing approach. Our proposed algorithms have potential use in various domains ranging from knowledge based frameworks to service composition, where the AND/OR structure is widely used for representing problems.

A Hybrid Test Architecture to Reduce Test Application Time in Full Scan Sequential Circuits

Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in test application time, because of serial loading of vectors. Although BIST based approaches offer faster testing, they usually suffer from low fault coverage. In this paper, we propose a hybrid test architecture, which achieves significant reduction in test application time. The test suite consists of: (i) some external deterministic test vectors to be scanned in, and (ii) internally generated responses of the CUT to be re-applied as tests iteratively, in functional (non-scan) mode. The proposed architecture uses only combinational ATPG to hybridize deterministic testing and test per clock BIST, and thus makes good use of both scan based and non-scan testing. We also present a bipartite graph based heuristic to select the deterministic test vectors and sequential fault simulation technique is used to perform the exact analysis on detected faults during the re-application of internally generated responses of the CUT during testing. Experimental results on ISCAS-89 benchmark circuits show the efficacy of the heuristic and reveal a significant reduction of test application time.

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture

Functional units supporting dynamic voltage and frequency scaling are being used today for fine grained power managed digital integrated circuits. The stringent power budget of these low power circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. Experimental results show that the algorithm that operates without any user constraint is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.

A Formal Method for Detecting Semantic Conflicts in Protocols between Services with Different Ontologies

The protocol between a web service and its client may lead to semantically inconsistent results if the ontologies used by the server and client are different. Given that the web is growing in a mostly uncoordinated way, it is unrealistic to expect that web services will adhere to standardized ontologies in near future. In this paper we show that if the client publishes its ontology and presents the protocol it intends to follow with a web service, then the web server can perform a semantic verification step to determine formally whether any of the possible executions of the protocol may lead to a semantic conflict arising out of the differences in their ontologies. We believe that this an approach which enables a web-server to automatically verify the semantic compatibility of a client with the service it offers before it actually allows the client to execute the protocol. We model the ontologies as graphs and present a graph based search algorithm to determine whether the protocol can possibly reach a conflict state.

Formal Guarantees for Localized Bug Fixes

Bug traces produced in simulation serve as the basis for patching the RTL code in order to fix a bug. It is important to prove that the patch covers all instances of the bug scenario; otherwise, the bug may return with a different valuation of the variables involved in the bug scenario. For large circuits, formal methods do not scale well enough to comprehensively eliminate the bug, and achieving adequate coverage in simulation and regression testing becomes expensive. This paper proposes formal methods for analyzing the control trace leading to the observed manifestation of the bug and verifying the robustness of the bug fix with respect to that control trace. We propose a classification of the bug fix based on the guarantee that our analysis can provide about the quality of the bug fix. Our method also prescribes the types of tests that are recommended to validate the bug fix on other types of scenarios. Since our methods are more scalable by orders of magnitude than model checking the entire design, we believe that the proposed formal methods hold immense promise in analyzing bug fixes in practice.

Inline Assertions - Embedding Formal Properties in a Test Bench

The scope of immediate assertions in SystemVerilog is restricted to Boolean properties, where as temporal properties are specified as concurrent assertions. Concurrent assertion statements can also be embedded in a procedural block - known as procedural concurrent assertions which are used under restricted situations. This paper introduces the notion of inline assertions which generalizes the embedding of temporal properties within the procedural code of a test bench. The paper proposes verification methodologies for inline assertions and compares them with the traditional approaches of formal property verification and dynamic assertion based verification. The paper also focuses on coverage related issues when the intent of a concurrent assertion is modeled as an inline assertion.

A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework

There has been a renewed interest in the operator scheduling problem due to the down-scaling trend of CMOS technology and the increasing adoption of the fine-grained power management at the level of individual functional unit. Traditionally branch-and-bound has been a popular choice for determining the pareto-optimal frontier with respect to area and power under certain user constraints. In this paper we explore the scope of parallelism within the branch-and-bound(B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. The scheduling also aims at maximum conditional and unconditional resource sharing and is able to attain sufficient area and power gains for complex benchmarks under strict and relaxed timing constraints. Experimental results reveals that the distributed framework is able to parallelize the search space uniformly and is able to achieve promising speedup compared to the serial B/B counterpart.

Cohesive Coverage Management: Simulation Meets Formal Methods

It has been advocated by many experts in design verification that the key to successful verification convergence lies in developing the verification plan with adequate formal rigor. Traditionally, the verification plans for simulation and formal property verification (FPV) are developed in different ways, using different formalisms, and with different coverage goals. In this paper, we propose a framework where the difference between formal properties and simulation test points is diluted by using methods for translating one form of the specification to the other. This allows us to reuse simulation coverage to facilitate formal verification and to reuse proven formal properties to cover simulation test points. We also propose the use of inline assertions in procedural (possibly randomized) test benches, and show that it facilitates the use of hybrid verification techniques between simulation and bounded model checking. We propose the use of promising combinations of formal methods presented in our earlier papers to shape a hierarchical verification flow where simulation and formal methods aim to cover a common design intent specification. The proposed flow is demonstrated using a detailed case study of the ARM AMBA verification benchmark. We believe that the methods presented in this work will stimulate new thought processes and ultimately lead to wider adoption of cohesive coverage management techniques in the design intent validation flow.