Vishal Choudhary

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107 GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. The 74mm2 IC is fabricated in 90nm CMOS.

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

Power Consumption of Performance-Scaled SIMD Processors

Single-Instruction Multiple-Data (SIMD) processing is valuable in numerous compute intensive application areas, especially in pixel processing on programmable processors. With SIMD, the nice thing is that the actual hardware can be scaled to the performance and the power consumption demands of the application domain, while the software suite remains equal. In this paper, we discuss the effect of scaling on power consumption, cost and performance which is related to the characteristics of applications ranging from mobile to medical video processing. Our analysis is based on experience obtained with the Philips Xetal SIMD processor [1,2].

Scalable IC platform for smart cameras

Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption). In this paper, we show that the combination of an SIMD (single-instruction multiple-data) processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon.

Formulation of SOC Test Scheduling as a Network Transportation Problem

Summary form only given. Reusability of tests is crucial for reducing total design time. This raises the problem of test knowledge transfer, physical test application and test scheduling. We present a formulation of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) as a network transportation problem. The problem is NP-hard and we present a O(mn(m+2n)) 2-approximation algorithm using the result of the single source unsplittable flow problem (U/sub FP/). We have implemented a Test Planner Tool TFLOW with the Common Lisp language using the U/sub FP/ algorithm given by Dinitz et al. (1999).

Efficient Stream Interface Topologies for Massively-Parallel SIMD Processing

Single-instruction multiple-data (SIMD) processing provides an efficient way to cope with the growing computational complexity of multi-media applications. One of the design challenges in massively-parallel SIMD architectures is the interface between the sequential input-output streams and the internal parallel compute engine. In this paper, three interface topologies are discussed and compared in terms of area, power and cycle overhead. Models are used to derive conclusions over the relative advantages among the topologies. Hybrid topologies that combine an SRAM and a vector register are proposed which provide more than factor two area saving with little power and cycle overhead penalty