Anthony D. Drumm

In the driver's seat of BooleDozer

The paper describes some of the synthesis controls in the BooleDozer synthesis system which are unique in concept and implementation. Rather than attempting to achieve the maximum amount of optimization in the minimum amount of run time, the designer specifies the restructuring level which allows him to specify to what extent the original structure should be preserved. We also describe controls which affect the mapping process. Finally we describe the incremental synthesis feature. The run time can be accurately controlled by a run-time budgeting mechanism.<<ETX>>

Fast and accurate wire delay estimation for physical synthesis of large ASICs

Interconnect delays represent an increasingly dominant portion of overall circuit delays. During timing-driven physical synthesis process, timing analysis is repeatedly performed over several hundred thousand components. Thus, fast and accurate estimation of interconnect delays is crucial. Traditionally, lumped and elmore delay models have been widely used for computing interconnect delays in physical synthesis due to their computational efficiency. However, these delay models are known to be inaccurate since they ignore slew and resistive shielding effects. In this paper, we propose a new iterative refinement based delay estimation approach that considers resistive shielding along with driver slew. Experimental results show that the proposed approach gives not only highly accurate results for far end RC-line delays but also compares very favorably to more difficult to match source end delays and source slews. In addition, use of the proposed delay model in physical synthesis yields significant performance improvement on several large industrial ASICs.