Anthony I. Chou

Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism

Stress-induced leakage current (SILC) in ultrathin oxide metal–oxide–semiconductor devices has been quantitatively modeled by the trap-assisted tunneling mechanism. These results are compared with experimental data on samples with oxide thickness ranging from 40 to 80 A. This model accurately describes the electric-field dependence of SILC, and also predicts the increase, then decrease in SILC, with decreasing oxide thickness, which is observed experimentally.

Optimization of sub 3 nm gate dielectrics grown by rapid thermal oxidation in a nitric oxide ambient

The vertical scaling of oxide thickness in the ultra large scale integrated era places stringent requirements on oxide quality. In this letter we report optimization studies in the growth of ultrathin oxynitrides in the sub 3 nm range. The oxynitride growth technique used involved self-limiting growth in nitric oxide (NO) followed by reoxidation in oxygen or nitrous oxide (N2O) ambient. This method allows tight control of oxide thickness and resulted in consistently low leakage currents over a range of thicknesses from 2 to 3 nm. The reliability of the oxynitrides is characterized using QBD, stress-induced leakage and surface charge and contact potential difference measurements. Charge-to-breakdown (QBD) data indicate that the reliability of the oxide degrades with increasing nitridation times in an NO ambient. Increasing reoxidation times in O2 have a similar effect. It is found that an improvement in reliability can be obtained by reoxidation in an N2O ambient. Surprisingly, reoxidizing in N2O proceeds ...

Plasma damage and photo-annealing effects of thin gate oxides and oxynitrides during O 2 plasma exposure

Plasma-induced damage effects of oxides and oxynitrides are studied using metal-oxide-semiconductor (MOS) test capacitors in an O/sub 2/ plasma environment inside a capacitive-coupled parallel plate RF etcher. Damage to both covered and sidewall-exposed samples are compared. As expected, it was found that as the exposure time was increased, more damage to the oxide was observed. Furthermore, N/sub 2/O-samples showed better immunity to O/sub 2/-plasma damage than the thermally grown O/sub 2/ samples during O/sub 2/ plasma exposure. However, the edge-intensive sidewall-exposed structures showed surprisingly less damage than the fully covered structures after a fixed plasma exposure time. This reduced damage effect for the sidewall-exposed structures is believed to be due to an in situ annealing as the result of the photoelectron injection by low-energy UV light interacting with the substrate. The in situ annealing does not occur in the fully covered structure since the low-energy UV light is blocked by the thick polysilicon gate. The results indicate that plasma damage evaluation using fully covered capacitors alone cannot be used to predict the actual damage in CMOS integrated circuits where there are almost always exposed thin oxide structures.

Improvement of ultrathin gate oxide and oxynitride integrity using fluorine implantation technique

The effects of fluorine on ultrathin gate oxide and oxynitride (∼40 A) have been studied. The incorporation of fluorine was done by fluorine ion implantation into polycrystalline silicon (polysilicon) gate followed by a high-temperature drive-in step. It has been found that the integrity of oxide has been improved with the incorporation of fluorine as demonstrated by the reduction of stress-induced leakage current and interface trap generation. Furthermore, unlike thicker dielectrics (>100 A) for which the charge-to-breakdown (QBD) values decrease with increasing fluorine concentration, QBD’s remain the same as those of the control samples for the ultrathin thickness regime. The mechanism for oxide quality improvement by F will also be discussed in the letter.

Reliability of gate oxide grown on nitrogen‐implanted Si substrates

Direct nitrogen implant into Si substrate prior to gate oxidation has been proposed to grow multiple gate oxide thicknesses on a single wafer. In this letter, we have studied the reliability of gate oxide grown on nitrogen‐implanted Si substrate. The effects of implant doses, sacrificial oxide thicknesses, and gate oxide thicknesses on gate oxide reliability have been investigated. It was found that there is a tradeoff between oxide thickness control and gate oxide reliability.

Optimization of gate dopant concentration and microstructure for improved electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides

We study the effects of gate dopant species (boron, arsenic, or phosphorous) concentration (1×1019 cm−3–1×1021 cm−3) and microstructure (as‐deposited amorphous or polycrystalline silicon gate) on the electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides (60 A). In order to minimize polysilicon depletion, a high gate dopant concentration is desirable. However, for devices with BF2 doped gates, it is found that because of boron penetration through the thin gate oxide, device characteristics degrade as the gate doping concentration increases, thus an intermediate gate doping must be chosen. In contrast, samples with arsenic and phosphorous doped gates show no degradation as the doping level increases. Optimization of gate microstructure for N2O and O2 dielectrics is also discussed.

Effect of BF2 implantation on ultrathin gate oxide reliability

BF2 implantation is widely used to form P wells, adjust channel threshold voltage, and reduce short channel effects. In this letter, we study effect of BF2 implantation on ultrathin gate oxide reliability. It has been found that BF2 implantation into Si substrate causes degradation of gate oxide reliability in the ultrathin oxide thickness regime. N2O oxide can be used to reduce degradation caused by the implantation and improve gate oxide reliability.

Effects of oxide exposure, photoresist and dopant activation on the plasma damage immunity of ultrathin oxides and oxynitrides

Plasma-induced damage study has been performed on ultrathin oxides and oxynitrides. Effects of oxide exposure, photoresist and gate dopant activation on the electrical and reliability characteristics were investigated. It was found that the sidewall exposed structures show less degradation in Qbd and trapping compared with fully covered MOSCAP structures after O/sub 2/ plasma exposure. A model for the damage mechanism was proposed which considers the radiation effect and photo-annealing effect, in addition to the well-known charging effect. Note that the damage induced might be very different in other plasma conditions because the photo-anneal effect is strongly dependent on the plasma condition. These results indicate that plasma damage evaluation using fully-covered capacitors alone cannot be used to predict the actual damages in CMOS integrated circuits. It was also found that photoresist overlayer protects the gate from charging and the induced damages will be reduced by activating the gate after the gate etch.

N2O-based tunnel oxides

Scaling down of the tunnel oxides allows reduction of the internal programming voltages and the memory cell size, and simplification of the peripheral circuit design related to highvoltage operation. However, several serious factors limit the scaling down of conventional thermal oxides. This includes the reduction in endurance which is related to charge trapping and time-dependent dielectric breakdown of the tunnel oxide. Leakage currents such as stressinduced leakage current and direct tunneling current are becoming a dominant factor as thicknesses are scaled down. Other factors that might limit the scaling of conventional thermally grown oxides include high defect and pinhole density which affect the manufacturing yield and device reliability, the ineffectiveness of thermal oxides in blocking diffusion of dopants, metals and impurities, excessive interface state density generation under various types of electrical and radiation stresses, and inadequate charge-to-breakdown and time-to-breakdown values. Furthermore, it has been reported that post-oxidation processes such as plasma exposure during metal etching can degrade thin oxides.