Jim Fulford

EFFECTS OF CHEMICAL COMPOSITION ON THE ELECTRICAL PROPERTIES OF NO-NITRIDED SIO2

The impact of nitrogen (N) concentration and distribution on the electrical and reliability properties of rapid‐thermally NO‐annealed oxides is studied. The use of NO‐annealing of thermally grown SiO2 provides an excellent way to isolate the effects of N, since this method allows for the incorporation of varying N profiles in the oxide without a simultaneous increase in dielectric thickness. Results show that the electrical properties of the dielectric under gate and substrate Fowler–Nordheim injection are highly sensitive to the N profile in the dielectric. While interface endurance (ΔDit) is seen to improve monotonically with increasing N concentrations for both +Vg and −Vg, the same is not observed for charge‐to‐breakdown (QBD) properties. It is found that although QBD improves with NO nitridation under +Vg, it shows a turnaround behavior under −Vg, i.e., for a 10‐s NO‐annealed oxide the QBD value is improved over control oxide while further nitridation is seen to degrade QBD under −Vg. The presence of bulk N and the nonuniform N distribution in the dielectric is responsible for this behavior.The impact of nitrogen (N) concentration and distribution on the electrical and reliability properties of rapid‐thermally NO‐annealed oxides is studied. The use of NO‐annealing of thermally grown SiO2 provides an excellent way to isolate the effects of N, since this method allows for the incorporation of varying N profiles in the oxide without a simultaneous increase in dielectric thickness. Results show that the electrical properties of the dielectric under gate and substrate Fowler–Nordheim injection are highly sensitive to the N profile in the dielectric. While interface endurance (ΔDit) is seen to improve monotonically with increasing N concentrations for both +Vg and −Vg, the same is not observed for charge‐to‐breakdown (QBD) properties. It is found that although QBD improves with NO nitridation under +Vg, it shows a turnaround behavior under −Vg, i.e., for a 10‐s NO‐annealed oxide the QBD value is improved over control oxide while further nitridation is seen to degrade QBD under −Vg. The presence of...

Degradation of oxynitride gate dielectric reliability due to boron diffusion

In this letter, we report on the impact of the suppression of boron diffusion via nitridation of SiO2 on gate oxide integrity and device reliability. SiO2 subjected to rapid thermal nitridation in pure nitric oxide (NO) is used to fabricate thin oxynitride gate dielectrics. Both n+ polycrystalline silicon (polysilicon) gated n‐MOS (metal–oxide semiconductor) and p+‐polysilicon gated p‐MOS devices were subjected to anneals of different times to study the effect of dopant diffusion on gate oxide integrity. As expected, an advanced oxynitride gate dielectric will effectively alleviate the boron‐penetration‐induced flatband voltage instability in p+‐polysilicon gated p‐MOS capacitors due to the superior diffusion barrier properties. However, such improvements are observed in conjunction with some degradation of the oxide reliability due to the boron‐blocking/accumulation inside the gate dielectric. Results show that even though the oxide quality is slightly degraded for NO‐nitrided SiO2 with p+‐polysilicon ga...

Correlation of dielectric breakdown with hole transport for ultrathin thermal oxides and N2O oxynitrides

In this letter, the dielectric breakdown characteristics of thermal oxides and N2O‐based oxynitrides have been studied. A direct correlation was found between dielectric breakdown and the hole current generated within the gate dielectrics. The dependence of dielectric breakdown on oxide thickness was also studied. It was found that both charge‐to‐breakdown and hole‐fluence‐to‐breakdown for the N2O oxynitrides were higher than those for the thermal oxides throughout the thickness range studied (33–87 A). The results suggest that N2O oxynitrides can sustain more damage before breakdown and thus have superior dielectric integrity compared to the thermal oxides.

‘‘Turn‐around’’ effects of stress‐induced leakage current of ultrathin N2O‐annealed oxides

Studies of the thickness dependence on stress‐induced leakage current (SILC) have been performed in the thickness range of 41 to 87 A for N2O‐annealed and O2‐grown oxides. N2O‐annealed oxide shows significantly reduced SILC leakage currents. Furthermore, SILC currents were found to increase with decreasing oxide thickness, as reported earlier. However, a ‘‘turn‐around’’ effect at ∼50 A has been observed in these films. SILC currents begin to decrease when oxide thickness is scaled below 50 A. This turn‐around effect can be explained using the trap‐assisted tunneling model. For thicknesses equal or less than 41 A, defect‐related current and direct tunneling current become dominant over SILC current. Our results indicated that for N2O‐based oxides in the ultrathin thickness regime, stress‐induced leakage currents become less significant.

Optimization of gate dopant concentration and microstructure for improved electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides

We study the effects of gate dopant species (boron, arsenic, or phosphorous) concentration (1×1019 cm−3–1×1021 cm−3) and microstructure (as‐deposited amorphous or polycrystalline silicon gate) on the electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides (60 A). In order to minimize polysilicon depletion, a high gate dopant concentration is desirable. However, for devices with BF2 doped gates, it is found that because of boron penetration through the thin gate oxide, device characteristics degrade as the gate doping concentration increases, thus an intermediate gate doping must be chosen. In contrast, samples with arsenic and phosphorous doped gates show no degradation as the doping level increases. Optimization of gate microstructure for N2O and O2 dielectrics is also discussed.

Hydrogen denudation for enhanced thin oxide quality, device performance, and potential epitaxial elimination

We report on the use of hydrogen denudation processing (annealing) that significantly improves CMOS bulk Cz wafer quality. Superior device performance, thin tunnel/gate oxide quality and Cz wafer surface properties have been measured demonstrating the potential for epitaxial elimination. This is achieved by subjecting the wafers to a short hydrogen denudation pre-process between 1050 C and 1200 C for 15 to 30 minutes. For thin oxides down to 8.2 nm up to 29% improvement was observed on two different QBD structures. Hydrogen denuding was also very effective in eliminating mode B oxide breakdown failures on bulk non-epitaxial Cz wafers. Additionally, an order of magnitude decrease in junction leakage was observed for the H/sub 2/ annealed wafers relative to the bulk non-epitaxial Cz wafers, resulting in bulk Cz wafers with surface properties similar to epi wafers without the added cost. SIMS and thermawave analysis coupled with an MeV phosphorus implant were used to characterize the effect of H/sub 2/ anneal on interstitial oxygen at the surface.<<ETX>>

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

Material processing and advanced well structures using high-energy implantation for EPI replacement

With the cost of each new technology generation increasing at an alarming rate, it has become imperative that technologies which provide for process simplification and material cost reduction be seriously investigated. Many of the next generation technologies for logic as well as memory applications have incorporated some vertical modulation of the well dopant concentration. This type of structure can provide process simplification and an improved isolation strategy, but with more aggressive engineering of the substrate dopant concentration and the current gain of the parasitic bipolar transistors that exist in the CMOS structure superior, latch-up immunity has been demonstrated on both simulated and actual devices. Devices with an aggressive 2 micron P+ to N+ spacing were built with this innovative well structure and have been shown to provide outstanding latch-up performance (4X improvement in measured trigger current) as compared to that of devices built with a standard diffused well process. In addition to providing an analysis of the latch-up performance of the advanced well structure, results of an investigation of the impact of high energy implantation on the gate oxide quality, junction quality and bulk material properties is discussed.

Role of SOG and oxynitride passivation in the field inversion of CMOS circuits

N-channel field inversion leakage in multi-level-metal CMOS precesses is one of the adverse effects of back-end-of-line (BEOL) processing. In particular, using certain combinations of nitride passivation films, Spin-On-Glass (SOG), and TEOS planarization was shown to be very detrimental to the stability of CMOS circuits because of the induced leakage under field oxides. This work reports on a new field inversion leakage that is totally due to silicon oxynitride passivation. The SOG film used to planarize the inter-metal dielectric (IMD) layers did not have a significant role in the field inversion leakage as we were able to induce and suppress the leakage currents by only controlling the oxynitride passivation deposition conditions (with and without the SOG). In particular it is shown that a high oxynitride deposition temperature induces sever parasitic leakage currents while a low deposition temperature diminished the leakage.