Kafai Lai

Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism

Stress-induced leakage current (SILC) in ultrathin oxide metal–oxide–semiconductor devices has been quantitatively modeled by the trap-assisted tunneling mechanism. These results are compared with experimental data on samples with oxide thickness ranging from 40 to 80 A. This model accurately describes the electric-field dependence of SILC, and also predicts the increase, then decrease in SILC, with decreasing oxide thickness, which is observed experimentally.

Correlation of dielectric breakdown with hole transport for ultrathin thermal oxides and N2O oxynitrides

In this letter, the dielectric breakdown characteristics of thermal oxides and N2O‐based oxynitrides have been studied. A direct correlation was found between dielectric breakdown and the hole current generated within the gate dielectrics. The dependence of dielectric breakdown on oxide thickness was also studied. It was found that both charge‐to‐breakdown and hole‐fluence‐to‐breakdown for the N2O oxynitrides were higher than those for the thermal oxides throughout the thickness range studied (33–87 A). The results suggest that N2O oxynitrides can sustain more damage before breakdown and thus have superior dielectric integrity compared to the thermal oxides.

‘‘Turn‐around’’ effects of stress‐induced leakage current of ultrathin N2O‐annealed oxides

Studies of the thickness dependence on stress‐induced leakage current (SILC) have been performed in the thickness range of 41 to 87 A for N2O‐annealed and O2‐grown oxides. N2O‐annealed oxide shows significantly reduced SILC leakage currents. Furthermore, SILC currents were found to increase with decreasing oxide thickness, as reported earlier. However, a ‘‘turn‐around’’ effect at ∼50 A has been observed in these films. SILC currents begin to decrease when oxide thickness is scaled below 50 A. This turn‐around effect can be explained using the trap‐assisted tunneling model. For thicknesses equal or less than 41 A, defect‐related current and direct tunneling current become dominant over SILC current. Our results indicated that for N2O‐based oxides in the ultrathin thickness regime, stress‐induced leakage currents become less significant.

Surface cleaning effect on dielectric integrity for ultrathin oxynitrides grown in N2O

In this study, we developed a wafer‐cleaning procedure for ultrathin dielectric growth. This involves a modified RCA clean, a dilute‐HF dip and a subsequent immersion in methanol/HF solution. Ultrathin (≊42 A) oxynitride films were grown in pure N2O using this new cleaning procedure and some other schemes to investigate the effects of surface preparation on dielectric integrity. Devices fabricated by this new cleaning procedure were found to exhibit the lowest leakage current level and the best breakdown performance among all samples. The variation in the current‐voltage characteristics across a 4‐in. wafer was also minimized by this two‐step dipping process. The results suggest that the new cleaning procedure is desirable to yield high‐quality ultrathin dielectrics.

Optimization of gate dopant concentration and microstructure for improved electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides

We study the effects of gate dopant species (boron, arsenic, or phosphorous) concentration (1×1019 cm−3–1×1021 cm−3) and microstructure (as‐deposited amorphous or polycrystalline silicon gate) on the electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides (60 A). In order to minimize polysilicon depletion, a high gate dopant concentration is desirable. However, for devices with BF2 doped gates, it is found that because of boron penetration through the thin gate oxide, device characteristics degrade as the gate doping concentration increases, thus an intermediate gate doping must be chosen. In contrast, samples with arsenic and phosphorous doped gates show no degradation as the doping level increases. Optimization of gate microstructure for N2O and O2 dielectrics is also discussed.

Effects of surface preparation on the electrical and reliability properties of ultrathin thermal oxide

A new wafer cleaning procedure has been developed for ultrathin thermal oxidation process (/spl les/50 /spl Aring/). It consists of a conventional RCA clean and a two-dip step, first in diluted HF and then in a methanol/HF solution, with no final DI water rinse. The effectiveness of this cleaning process has been compared to other commonly used cleaning methods, based on the dielectric integrity of the ultrathin thermal oxide grown. It has been found that this two-dip method produces oxides with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxide. Furthermore, this new procedure increases dielectric breakdown field, E/sub bd/ and charge-to-breakdown, Q/sub bd/ (both intrinsic and defect-related values) of ultrathin oxides. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen and the reduced surface micro-roughness.<<ETX>>

Effects of oxide exposure, photoresist and dopant activation on the plasma damage immunity of ultrathin oxides and oxynitrides

Plasma-induced damage study has been performed on ultrathin oxides and oxynitrides. Effects of oxide exposure, photoresist and gate dopant activation on the electrical and reliability characteristics were investigated. It was found that the sidewall exposed structures show less degradation in Qbd and trapping compared with fully covered MOSCAP structures after O/sub 2/ plasma exposure. A model for the damage mechanism was proposed which considers the radiation effect and photo-annealing effect, in addition to the well-known charging effect. Note that the damage induced might be very different in other plasma conditions because the photo-anneal effect is strongly dependent on the plasma condition. These results indicate that plasma damage evaluation using fully-covered capacitors alone cannot be used to predict the actual damages in CMOS integrated circuits. It was also found that photoresist overlayer protects the gate from charging and the induced damages will be reduced by activating the gate after the gate etch.

Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (<EQ 50 angstrom). This involves a modified RCA clean and a two-step dip, first in diluted HF and then in a methanol/HF solution, with no final DI water rinse. Ultrathin thermal oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

N2O-based tunnel oxides

Scaling down of the tunnel oxides allows reduction of the internal programming voltages and the memory cell size, and simplification of the peripheral circuit design related to highvoltage operation. However, several serious factors limit the scaling down of conventional thermal oxides. This includes the reduction in endurance which is related to charge trapping and time-dependent dielectric breakdown of the tunnel oxide. Leakage currents such as stressinduced leakage current and direct tunneling current are becoming a dominant factor as thicknesses are scaled down. Other factors that might limit the scaling of conventional thermally grown oxides include high defect and pinhole density which affect the manufacturing yield and device reliability, the ineffectiveness of thermal oxides in blocking diffusion of dopants, metals and impurities, excessive interface state density generation under various types of electrical and radiation stresses, and inadequate charge-to-breakdown and time-to-breakdown values. Furthermore, it has been reported that post-oxidation processes such as plasma exposure during metal etching can degrade thin oxides.