Anthony M. Hill

A 600-MHz VLIW DSP

A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at 0.3 mW/MMAC (16 b). The chip has 64 M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an 8-way VLIW DSP core, a 2-level memory system, and 2.4 GB/s I/O bandwidth. The DSP chip is implemented in 0.13 μm CMOS technology with 6-layer copper metalization.

BEOL variability and impact on RC extraction

Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure

The combined processing power of three 1+GHz DSP cores and 65nm 7M CMOS integration delivers a WCDMA macro base-station on a single chip. The 300M transistor IC can perform up to 24000MIPS, 8000 16b MMACs per second, coupled with symbol-rate and chip-rate acceleration and dissipates less than 6W.

Design techniques for high performance, energy efficient control logic

This paper investigates delay, power and area of critical components in designing energy-efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30%. For multiplexers (MUX) three MUXes are proposed and compared to existing solutions. The proposed MUXes improve performance by 50% or power by 22%. The impact of scaling supply voltage alone and scaling threshold voltage with supply voltage on delay and power is also examined.

Hybrid dual-threshold design techniques for high-performance processors with low-power features

This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18-/spl mu/m technology at a supply voltage of 1.8 V, the proposed hybrid dual-V/sub t/ (HDVT) circuit architectures enhance speed of low-V/sub t/ by 21% while reducing leakage power dissipation of low-V/sub t/ by an order of magnitude for combinatorial logic. For sequential elements, a HDVT split-slave dual-path (HSSDP) and Push-Pull Isolation (HPPI) registers are proposed to improve 29-92% performance over an HDVT-conventional registers with 20-89% less energy consumption. For the datapath, a HDVT hierarchical, reduced-swing, dual-V/sub t/ logic (HHRSL) comparator is proposed to improve the delay of prior arts by up to 50%.

Impact of interconnect technology scaling on SOC design methodologies

The impact of interconnect technology scaling on RC delay is a well-researched topic. This paper provides a fresh perspective on the impact of interconnect technology scaling on SOC designs. The impact of intra-cell RC parameters on circuit performance is described. The importance of managing the intra-cell RC scaling for low power designs is emphasized. The impact of fill metal and CMP on analog circuits is illustrated. The significance of accurate RC extraction for validating the performance and signal integrity of SOC designs is discussed. Using a 64M transistor SOC design, the effects of noise and EM reliability are highlighted. The impact of inductance on clock skew, noise and reliability are discussed.

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.

SmartExtract: accurate capacitance extraction for SOC designs

Most capacitance extraction tools used in SOC designs use 2.5D methods and suffer from inherent limitations in accuracy. Often accuracy is traded off in lieu of runtime. In addition, every net in a design is extracted to same level of accuracy. As interconnect RC is a significant portion of circuit performance, errors in capacitance extraction directly affects the maximum attainable chip frequency. In this paper, a new methodology for accurate capacitance extraction called SmartExtract is described. Not all nets in a design need high degree of capacitance extraction accuracy. SmartExtract exploits this scenario and enables selective accuracy of extraction based on timing criteria. Application of this methodology to 90nm and 65nm DSP designs is described.

A 800 MHz system-on-chip for wireless infrastructure applications

The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.

Heterogeneous Multi-processor Coherent Interconnect

The rapid increase in processor and memory integration onto a single die continues to place increasingly complex demands on the interconnect network. In addition to providing low latency, high speed and high bandwidth access from all processors to all shared resources, the burdens of hardware cache coherence and resource virtualization are being placed upon the interconnect as well. This paper describes a multi-core shared memory controller interconnect (MSMC) which supports up to 12 processors, 8 independent banks of IO-coherent on-chip shared RAM, an IO-coherent external memory controller, and high bandwidth IO connections to the SoC infrastructure. MSMC also provides basic IO address translation and memory protection for the on-chip shared SRAM and external memory as well as soft error protection with hardware scrubbing for the on-chip memory. MSMC formed the heart of the compute cluster for a 28-nm CMOS device including 8 Texas Instruments C66x DSP processors and 4 cache-coherent ARM A15 processors sharing 6 MB of on-chip SRAM running at 1.3 Ghz. At this speed MSMC provides all connected masters a combined read/write bandwidth of nearly 1TB/s to access a combined read/write bandwidth of 457.6 GB/s to all shared resources @ 16 mm2.