Jose Luis Flores

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.

A 800 MHz system-on-chip for wireless infrastructure applications

The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.

Reconfigurable array media processor (RAMP)

This paper presents the architecture of a Reconfigurable Array Media Processor (RAMP). RAMP features a 2D array of coarse-grained configurable logic blocks (CLBs) connected together by local and global inter-connects. The CLBs on RAMP provide a 4-bit ALU, 2/spl times/2 bit parallel multiply function, 4-bit barrel shifter, two 4-bit registers and a local programmable control unit. RAMP is capable of partial run-time reconfiguration and supports block-mode reconfiguration. The novel features of this device include two programmable high-speed clocks available to each CLB, scalable parallel multiplier, on-chip memory/registers. RAMP can be used to implement high-performance computational kernals of video, audio and signal processing functions. Matrix multiplication, FIR filters and Inverse DCT functions are used as examples to demonstrate the capabilities of the RAMP architecture.

Perils of power prediction in early power-integrity analysis

Early power integrity and peak power analyses for multi-million gate system on chip (SoC) in advanced technology nodes pose significant methodology definition and implementation challenges. Typically in a SoC, processors and other high performance IPs are dominant contributors to peak power and power integrity issues. To get an early look ahead of potential power integrity issues and to estimate peak di/dt issues in the SoC, it is always desired to analyze potential issues early and address before a silicon failure. This paper presents an overview of implementation challenges faced in RTL based power for predictive power analysis and analyzing peak di/dt issues ahead of time in the context of TI C66× DSP core based multicore SoC.