Antoine Frappe

A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS

This paper presents a low-power mixed-signal adaptive 60 GHz baseband in 65 nm CMOS. The design integrates variable gain amplifiers, analog phase rotator, 40-coefficient I/Q decision feedback equalizers (DFEs), clock generation and data recovery circuits, and adaptation hardware. The baseband achieves 10 Gb/s operation with BER <; 10-12 while consuming 53 mW (adaptation on)/45 mW (adaptation off), of which the core signal processing circuits consume only 29 mW.

Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters

This paper presents a very high-speed delta-sigma modulator for achieving digital generation of radio-frequency signals. About 68 dB of ACLR (adjacent channel leakage ratio) is obtained on the 7.8 GS/s output of the delta-sigma modulator for WCDMA standard. This is achieved by using original concepts like borrow-save arithmetic, non-exact quantization and differential dynamic logic.

A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner

This paper presents a reconfigurable semi-digital RFFIR filter suitable for digital transmitters using 1-bit DeltaSigma signal generation. A transmission line based 5-channel power combiner allows both increase of output power and programmable filtering of the signal. A prototype has been built with 65 nm CMOS and Integrated Passive Devices (IPD) technologies. The system exhibits a 14 dB power gain for a peak power of 17 dBm at 1.2 GHz and an attenuation of out-of band noise of up to 15 dB. CMOS and IPD chip size are respectively 2.05 mm2 and 17.78 mm2.

A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters

This paper presents the design and measurement of a 4 × oversampled 18th order digital low-pass FIR filter. It is a key building block in the proposed digitally enhanced transmitter architecture for 60 GHz wireless high-data rate links. Spectrum mask requirements are fully satisfied for OFDM modulated signals without requiring additional analog filtering. Pipelined CPL adders and TSPC flip-flops are used to enable a very high operation frequency. The core area is 0.1 mm2 in a standard GP 65 nm CMOS process. Measured power consumption is 400 mW at 9.6 GS/s with a 1.4 V power supply voltage.

All-digital RF signal generation for software defined radio

Digital generation of radio-frequency signals is a key concept of software defined radios. This paper presents a digital transmitter chain including a very high-speed delta-sigma modulator. It comprises also baseband processing, sample rate conversion, digital upconverter and output stages (switching- mode amplifier and BAW filters). About 74 dB of ACLR (adjacent channel leakage ratio) is obtained on the 7.8 GS/s output of the delta-sigma modulator for the WCDMA standard.

A digital ΔΣ RF signal generator for mobile communication transmitters in 90nm CMOS

The presented digital RF signal generator in 90 nm CMOS uses 1-bit DeltaSigma modulation and targets mobile communication terminals. A 50 MHz bandwidth centered on 1 GHz can be achieved when the circuit is clocked at 4 GHz. Signals up to 3 GHz can be synthesized when using the first image band. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. The digital core employs redundant arithmetic, precomputed non-exact quantization and differential dynamic logic. The digital core consumes 49 mW at maximum clock frequency. Active area is 0.15 mm2.

A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications

This paper presents the theoretical analysis and simulation results of an IF to DC subsampler for 60 GHz heterodyne receivers architectures. A particular arrangement of the frequency plan allows embedded anti-alias filtering. Down-conversion, channel filtering and IQ demodulation are merged into a unique operation at no extra cost in terms of area and power consumption. The adjacent and alternate channel rejections for the 802.15.3.c are respectively more than 15 dBc and 23 dBc thanks to charge domain subsamplers. This paper presents solutions for the implementation of the system and its integration into a complete 60 GHz receiver. Advanced analysis is made for critical points of the architecture: generation of the integration windows, IQ demodulation, noise folding and effect of clock jitter. The proposed architecture is validated by simulations and complies with the requirements of the standards for 60 GHz wireless communications. The result of this study shows that sub-sampling is suitable for high bandwidth and high data-rate receiver systems.

A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards

IEEE 802.11ac (WiFi) and IEEE 802.11ad (60-GHz WiGig) are emerging gigabit-per-second standards providing complementary services but different nature of signals. The 802.11ac targets high-resolution and narrow-to-medium bandwidth channels, while 802.11ad aims to provide broadband communications with simple modulation schemes. This work proposes a single-physical-layer transmitter baseband architecture for both 11ac and 11ad standards. The core of the proposed transmitter is a configurable mixed-signal digital-to-analog converter (DAC), which has an embedded semidigital filtering tailored for four WiFi modes (20, 40, 80, and 160 MHz) and the 1.76-GHz bandwidth of the 60-GHz WiGig standard. The DAC operates on the oversampled WiFi and raw WiGig data at a common 3.52-GHz clock frequency. System-level simulations of the finite impulse response DAC-based architecture show that the requirements of the standards can be met with maximum hardware sharing and reduced area penalty.

Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulators configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.

Reconfigurable complex digital Delta-Sigma modulator synthesis for digital wireless transmitters

Digital generation of radio-frequency signals is a key concept of software defined radio. One of the main difficulties for multi-standard transmitter design based on delta-sigma (DeltaSigma) modulators is to respect the different specifications in terms of out-of-band spurious emission. Focusing on the TX path of a UMTS/DCS1800 mobile phone, we propose hereinafter an efficient method aiming at synthesizing a complex 5th-order DeltaSigma modulator which respects the targeted standards spurious specifications. The use of a complex noise transfer function allows a better optimization of noise shaping. In addition, this approach eases the reconfiguration of the modulator, and, it is a powerful tool for all order (real and complex) DeltaSigma modulators synthesis, as it will be illustrated.