António Canelas

Floorplan-aware analog IC sizing and optimization based on topological constraints

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE?, Eldo? or Spectre?) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130nm design process. Fast floorplan generation using topological constraints for circuit synthesis.Usage of multiple templates to increase the floorplan quality.Wide range of solutions obtained from the multi-objective circuit optimization.Complete design flow demonstrated for the UMC 130nm design process.Circuit evaluation using the industrial simulators tool (ELDO, HSPICE, Spectre).

A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques

This paper presents a new computational finance approach, combining a Symbolic Aggregate approXimation (SAX) technique together with an optimization kernel based on genetic algorithms (GA). The SAX representation is used to describe the financial time series, so that, relevant patterns can be efficiently identified. The evolutionary optimization kernel is here used to identify the most relevant patterns and generate investment rules. The proposed approach was tested using real data from S&P500. The achieved results show that the proposed approach outperforms both B&H and other state-of-the-art solutions.

AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation

This paper presents AIDA 2015, the newest version of AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the AIDA environment, www.aidasoft.com, is demonstrated for analog IC design, sizing and layout generation, using state-of-the-art technologies, and validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO ®, or CALIBRE®.

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Abstract This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.

A new SAX-GA methodology applied to investment strategies optimization

This paper presents a new computational finance approach, combining a Symbolic Aggregate approXimation (SAX) technique together with an optimization kernel based on genetic algorithms (GA). The SAX representation is used to describe the financial time series, so that, relevant patterns can be efficiently identified. The evolutionary optimization kernel is here used to identify the most relevant patterns and generate investment rules. The proposed approach was tested using real data from S&P500. The achieved results show that the proposed approach outperforms both B&H and other state-of-the-art solutions.

LC-VCO automatic synthesis using multi-objective evolutionary techniques

Typically the design of oscillators is done aiming at both minimum phase noise and minimum power consumption, however, these two objectives are contradictory. Yet, this tradeoff, which is also the base for the definition of the figure of merit of oscillators, is seldom explored is previous publications. In this paper, an LC-Voltage Controlled Oscillator (VCO) was considered in a multi-objective optimization process, where the accuracy and reliability of the solution is guaranteed by the usage of a circuit simulator to evaluate the circuit performance. The state-of-the-art circuit optimization tool AIDA-C was used in the automatic synthesis of the LC-VCO, obtaining a set of about 40 design solutions with FOM bellow -191 dBc/Hz, where the power consumption varies from 0.22 to 0.46 mW and the phase noise varies from -120.47 to -116.72 dBc/Hz.

Extraction and application of wiring symmetry rules to route analog multiport terminals

In this paper an innovative routing methodology considering wiring symmetry (WS) for multiport multiterminal (MP/MT) signal nets of analog and mixed-signal integrated circuits (ICs) is presented. In our work, first, an electromigration (EM)-aware wiring topology for each power and signal network is constructed directly from the netlist, and then, several embedded symmetry rules between wires are automatically identified and applied in the global and detailed routing phases. The use of such MP terminals strongly enhances both the ability to route the circuit and the WS. The design flow is demonstrated for the UMC 130nm design process.

Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness

This paper proposes a new Multi-Dimensional SAX-GA approach to pattern discovery using genetic algorithms (GA). The approach is capable of discovering patterns in multi-dimensional financial time series. First, the several dimensions of data are converted to a Symbolic Aggregate approXimation (SAX) representation, which is, then, feed to a GA optimization kernel. The GA searches for profitable patterns occurring simultaneously in the multi-dimensional time series. Based on the patterns found, the GA produces more robust investment strategies, since the simultaneity of patterns on different dimensions of the data, reinforces the strength of the trading decisions implemented. The proposed approach was tested using stocks from S&P500 index, and is compared to previous reference works of SAX-GA and to the Buy & Hold (B&H) classic investment strategy.

Grounded active inductors design optimization for fQmax = 14.2GHz using a 130 nm CMOS technology

This paper presents a novel design of an active inductor based on the topology of Manetakis regulated cascode active inductor. The aim of this work is to enhance the manual design of active inductors by using AIDA-C design automation methodology. The circuit is manually designed using a 130 nm CMOS technology in Cadence® to obtain an Inductor operating at 14.2GHz. The sizing of the proposed active inductor has later been optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. The AIDA-C circuit sizing tool was able to achieve active inductors solutions with higher quality factor, higher inductance at the operating frequency and also higher bandwidth than the manually designed solution, with the additional surplus of presenting a set of alternative Pareto optimal solutions that enables the designer to choose the most suitable circuit.

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations

This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required MC simulations during the optimization process. The simulated solutions are the most likely to populate the Pareto optimal front and result from a selection process based on a modified k-means algorithm. The proposed approach leads 75% reduction in the total number of the MC simulations for the presented case study.