Nuno Horta

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

Applying a GA kernel on optimizing technical analysis rules for stock picking and portfolio composition

The management of financial portfolios or funds constitutes a widely known problematic in financial markets which normally requires a rigorous analysis in order to select the most profitable assets. The presented paper proposes a new approach, based on Intelligent Computation, in particular genetic algorithms, which aims to manage a financial portfolio by using technical analysis indicators (EMA, HMA, ROC, RSI, MACD, TSI, OBV). In order to validate the developed solution an extensive evaluation was performed, comparing the designed strategy against the market itself and several other investment methodologies, such as Buy and Hold and a purely random strategy. The time span (2003–2009) employed to test the approach allowed the performance evaluation under distinct market conditions, culminating with the most recent financial crash. The results are promising since the approach clearly beats the remaining approaches during the recent market crash.

LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits

This paper describes an innovative design automation tool, LAYGEN II, for analog integrated circuit (IC) layout generation based on template descriptions and on evolutionary computation techniques. LAYGEN II was developed giving special emphasis to the reusability of expert knowledge and to the efficiency of retargeting operations. The designer specifies the sized circuit-level structure, the required technology and also, the layout template consisting of technology and specification independent high-level layout guidelines. For placement, the topological relations present in the template are extracted to a nonslicing B*-tree layout representation, and the tool automatically merges devices and improves the floorplan quality. For routing an optimization kernel consisting of a tailored version of the multiobjective multiconstraint evolutionary algorithm NSGA-II is used. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.

Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques

The microelectronics market trends present an ever-increasing level of complexity with special emphasis on the production of complex mixed-signal systems-on-chip. Strict economic and design pressures have driven the development of new methods to automate the analog design process. However, and despite some significant research efforts, the essential act of design at the transistor level is still performed by the trial and error interaction between the designer and the simulator. This book presents a new design automation methodology based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals

A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper. This modulator was designed to cope with six different communications standards relying on a flexible architecture. Furthermore, the proposed architecture introduces the ability to process concurrently two different signals. The major design issues are outlined and operation modes are detailed. The feasibility of the presented solution is demonstrated using high-level system-level simulations as well as device-level simulations of the modulator implemented with switched capacitor circuits.

AIDA: Automated analog IC design flow from circuit level to layout

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to a physical layout description. AIDA results from the integration of two in-house tools, namely, GENOM-POF and LAYGEN II. GENOM-POF performs fully automated circuit-level synthesis implemented with a multi-objective multi-constraint optimization approach, which addresses robust design requirements by considering Corners analysis together with an electrical simulator as the evaluation engine. LAYGEN II implements a DRC proved fully automated layout generation based on a sized circuit-level description and high level layout guidelines, described in a technology independent abstract layout template. The expert knowledge is used by LAYGEN II to guide the evolutionary optimization kernels during the automatic layout generation. Moreover, evolutionary computation techniques are extensively used, at both circuit-level and physical-level, as tool to solve design optimization problems. Finally, AIDA environment is demonstrated for the IC design of a classical circuit-level topology and state-of-the-art technology, and validated by industrial simulators and analysis tools, such as, HSPICE® and CALIBRE®.

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation

In this paper, a multi-objective design methodology and tool for automatic analog IC synthesis, which takes into account the effects of process variations, is presented. By varying the technological and environmental parameters, the robustness of the solutions is enhanced. The automatic analog IC sizing tool, GENOM-POF, was implemented to demonstrate the methodology and to verify the effects of corner cases on the Pareto optimal front (POF). The impacts of NSGA-II parameters when applied to analog circuit sizing were investigated, and three different design strategies were tested in a benchmark circuit, showing the effectiveness of multi-objective design of analog cells.

Floorplan-aware analog IC sizing and optimization based on topological constraints

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE?, Eldo? or Spectre?) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130nm design process. Fast floorplan generation using topological constraints for circuit synthesis.Usage of multiple templates to increase the floorplan quality.Wide range of solutions obtained from the multi-objective circuit optimization.Complete design flow demonstrated for the UMC 130nm design process.Circuit evaluation using the industrial simulators tool (ELDO, HSPICE, Spectre).

A multi-objective routing algorithm for Wireless Multimedia Sensor Networks

Graphical abstractDisplay Omitted HighlightsA new multi-objective approach for the routing problem in Wireless Multimedia Sensor Networks (WMSNs) is proposed.Classical approximations optimize a single objective or Quality of Service (QoS) parameter.Classical approximations do not take into account the conflicting nature of QoS parameters which leads to sub-optimal solutions.The proposed approach takes into account multiple QoS requirements such as delay and the Expected Transmission Count (ETX).The case studies applying the proposed approach shows clear improvements on the QoS routing solutions. In this paper, a new multi-objective approach for the routing problem in Wireless Multimedia Sensor Networks (WMSNs) is proposed. It takes into account Quality of Service (QoS) requirements such as delay and the Expected Transmission Count (ETX). Classical approximations optimize a single objective or QoS parameter, not taking into account the conflicting nature of these parameters which leads to sub-optimal solutions. The case studies applying the proposed approach show clear improvements on the QoS routing solutions. For example, in terms of delay, the approximate mean improvement ratios obtained for scenarios 1 and 2 were of 15 and 28 times, respectively.

GA-SVM feasibility model and optimization kernel applied to analog IC design automation

An efficient use of macromodeling techniques is pointed out as an effective approach to improve the convergence and speed of the optimization process. The methodology presented in this paper is based on a learning scheme using Support Vector Machines(SVMs) that together with and an evolutionary strategy is used to create efficient models to estimate and optimize the performance parameters of analog and mixed-signal ICs. The SVM is used to identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization based methodology is demonstrated for the design of a well known class of CMOSoperational amplifier topologies. The efficiency of the proposed approach is compared with standard and modified genetic algorithm kernels.