Ricardo Povoa

Floorplan-aware analog IC sizing and optimization based on topological constraints

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE?, Eldo? or Spectre?) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130nm design process. Fast floorplan generation using topological constraints for circuit synthesis.Usage of multiple templates to increase the floorplan quality.Wide range of solutions obtained from the multi-objective circuit optimization.Complete design flow demonstrated for the UMC 130nm design process.Circuit evaluation using the industrial simulators tool (ELDO, HSPICE, Spectre).

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners

This paper presents the design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz-pF/mA has been achieved).

AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation

This paper presents AIDA 2015, the newest version of AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the AIDA environment, www.aidasoft.com, is demonstrated for analog IC design, sizing and layout generation, using state-of-the-art technologies, and validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO ®, or CALIBRE®.

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Abstract This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques

Typically the design of a Radio-Frequency (RF) circuit is difficult, time-consuming and often based around an iterative process. In this manuscript, an automatic synthesis of three typical blocks of nowadays RF front-end receivers, a narrowband differential low-noise amplifier, a mixer and a local oscillator, is presented. The synthesis of the three circuits was made at sizing level and was carried out by Analog IC Design Automation (AIDA). AIDA is a multi-objective multi-constraint simulator based automatic IC design tool, which optimizes analog circuits through the usage of evolutionary computation. The performance potential of the circuits and tool is evaluated through electrical simulation results, which are finally compared with recently published state-of-the-art works, with overall better results and little time-consumption, proving the surplus value of using an automatic IC design tool in RF circuitry synthesis. Automatic RF circuits sizing, using UMC 130 nm technologyMultiobjective multiconstraint simulator-based optimization approachProposal of a new LNA topology and complete description of the circuitsComplete description of the optimization flowCircuit evaluation using industrial simulators

LC-VCO automatic synthesis using multi-objective evolutionary techniques

Typically the design of oscillators is done aiming at both minimum phase noise and minimum power consumption, however, these two objectives are contradictory. Yet, this tradeoff, which is also the base for the definition of the figure of merit of oscillators, is seldom explored is previous publications. In this paper, an LC-Voltage Controlled Oscillator (VCO) was considered in a multi-objective optimization process, where the accuracy and reliability of the solution is guaranteed by the usage of a circuit simulator to evaluate the circuit performance. The state-of-the-art circuit optimization tool AIDA-C was used in the automatic synthesis of the LC-VCO, obtaining a set of about 40 design solutions with FOM bellow -191 dBc/Hz, where the power consumption varies from 0.22 to 0.46 mW and the phase noise varies from -120.47 to -116.72 dBc/Hz.

Current-flow and current-density-aware multi-objective optimization of analog IC placement

Abstract In this paper, the concept of hierarchical multi-objective optimization is applied to analog integrated circuit placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce post-layout routing-induced parasitics of the circuit. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration-aware optimization of the optimal wiring topology for all nets of the circuit. The problem׳s complexity is reduced using the hierarchy in the circuit׳s partitions, combining, bottom-up, Pareto fronts of placements that explore the tradeoffs between the design objectives. The approach is demonstrated in analog circuit structures for the United Microelectronics Corporation 130xa0nm design process. Post-layout simulations show the importance of considering both current-flow and current-density considerations for an effective fully-automatic placement.

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner

This paper presents the design and the electrical simulations of a single-stage amplifier with high energy-efficiency and enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, a fully-differential folded voltage-combiner block is used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of the properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 50 dB can be achieved, together with high energy efficiency. A simulated figure-of-merit above 2200 MHz×pF/mA has been reached. The circuit was designed using a 130 nm CMOS technology, draining approximately 0.2 mA from a 1.2 V power supply.

Grounded active inductors design optimization for fQmax = 14.2GHz using a 130 nm CMOS technology

This paper presents a novel design of an active inductor based on the topology of Manetakis regulated cascode active inductor. The aim of this work is to enhance the manual design of active inductors by using AIDA-C design automation methodology. The circuit is manually designed using a 130 nm CMOS technology in Cadence® to obtain an Inductor operating at 14.2GHz. The sizing of the proposed active inductor has later been optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. The AIDA-C circuit sizing tool was able to achieve active inductors solutions with higher quality factor, higher inductance at the operating frequency and also higher bandwidth than the manually designed solution, with the additional surplus of presenting a set of alternative Pareto optimal solutions that enables the designer to choose the most suitable circuit.

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis

This paper presents a new approach to enhance a state-of-the-art layout-aware analog IC circuit-level optimizer, by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on a modified NSGA-II algorithm. The gradient model is automatically generated by, first, using a design of experiments (DOE) approach with two alternative sampling strategies, the full factorial design and the fractional factorial design, which define the samples that will be accurately evaluated using a circuit simulator (e.g. HSPICE®), second, extracting and ranking the contributions of each design variable to each performance measure or objective, and, finally, building the model based on series of gradient rules. The gradient model is then embedded into the modified NSGA-II optimization kernel, by acting on the mutation operator. The approach was validated with typical analog circuit structures for an industry standard 0.13 μm integration process, showing that, by enhancing the circuit sizing evolutionary kernel with the gradient model, the optimal solutions are achieved, considerably, faster and with identical or superior accuracy.