Antonio Ciccomancini Scogna

Equivalent network synthesis for via holes discontinuities

A methodology is presented for the synthesis of the passive equivalent circuit of via holes in multilayer printed circuit boards. The paper describes the network synthesis starting from the extraction of the poles and residues from the driving point transfer functions for two port networks. The via hole is partitioned into elementary structures assumed not electromagnetically coupled and the scattering parameters for each one of them are evaluated by using a numerical approach suitably validated by comparison with results computed by other independent numerical methods. The equivalent circuit of the complete via hole is given by the cascading of the circuits of the elementary structures. The proposed technique is validated by comparing the computed scattering parameters with those from measurements for real test boards.

S-parameters characterization of through, blind, and buried via holes

A method for de-embedding the scattering parameters matrix for single-end or differential through, buried, and blind via holes in multilayer printed circuit boards for high-speed digital applications is presented. The proposed technique starts from a measurement or simulation of the structure containing the discontinuity and, after the structures partitioning, extracts the scattering parameters of the required discontinuity. The procedure is applied to different kinds of single-ended and differential via holes and is validated by measurements. The finite integration technique is used to perform the needed three-dimensional electromagnetic simulations. Due to its reduced CPU time, the proposed methodology is suitable for a parametric analysis on the electrical performance of the via hole discontinuities and it gives useful results for the extraction of accurate computer-aided design models.

Bandwidth Enhancement Based on Optimized Via Location for Multiple Vias EBG Power/Ground Planes

The ground surface perturbation lattice (GSPL) structure is investigated to suppress power noise in the power distribution network of mixed signal circuits. In order to enhance the bandwidth of the noise suppression, the GSPL structure is implemented by using multiple vias in the mushroom-like electromagnetic bandgap structure. Under the concept of multiple vias, the lower and upper bound cutoff frequencies of the bandgap are influenced by the position of the vias. An optimum position for the vias is found to achieve maximum stopband bandwidth. In this paper, the stopband mechanism of GSPL structure is investigated and the corresponding equivalent circuit model is proposed to quickly predict the lower and upper bound cutoff frequencies. Suitable test boards are fabricated and measured to demonstrate the accuracy of the design concept. The result shows that there is a good consistency between simulated, modeled, and measured results.

De-embedding procedure based on computed/measured data set for pcb structures characterization

This paper uses a de-embedding procedure, based on measured and numerically computed S-parameters, to obtain the characterization of portions of a structure difficult to obtain by direct measurements. The results are validated by measurements and independent calculations.

Design and modeling for chip-to-chip communication at 20 Gbps

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

Grounding, unbalancing and length effects on termination voltages of a twinax cable during bulk current injection

By means of an equivalent SPICE circuit of a two-parallel-wires shielded cable (twinax), the effects on the induced voltages at the cables terminations during a bulk current injection are studied for different shields grounding, different cables asymmetries or unbalancing and different lengths of the cable. The analysis is carried out both in frequency and time domain.

Enabling terabit per second switch linecard design through chip/package/PCB co-design

Widespread use of the Web 2.0 Internet applications such as video streaming and social networking are continuously demanding higher bandwidth network equipment. Electrical designers increasingly face more and more challenges to deliver higher speed products within short development cycle due to design complexity and new multi-GHz signal integrity problems. This paper presents a modeling and simulation methodology through chip/package/PCB (printed circuit board) co-design and co-optimization to enable a terabit per second network switch linecard design. Channel design techniques such as BGA (Ball Grid Array) pin backdrill, via tuning, and low loss interconnects are outlined. Full wave 3D modeling techniques with optimal model segmentation, model cascading and model optimization are discussed. At the end, correlation between lab measurement and simulation in both frequency and time domains are investigated.

A comparative study of PEEC circuit elements computation

A key use of the PEEC method is the solution of combined electromagnetic and circuit problems as they occur in many situations in todays very large scale integrated circuits (VLSI) and systems. An important aspect of this approach is the fast and accurate computation of PEEC circuit matrix elements, the partial inductances and normalized coefficients of potential. Recently, fast multipole methods (FMM) have been applied to the PEEC method in the frequency domain as a way to speed up the solution. In this paper, we consider the fast evaluation of the PEEC circuit matrix elements by two different methods, a matrix version of the (FMM) PEEC method and a method, which we call the fast multi-function (FMF) PEEC approach. In this technique, the matrix coefficients are evaluated using analytical functions approximation of the coefficients in combination with a proper choice of numerical quadrature formulas.

Experimental validation of circuit models for bulk current injection (BCI) test on shielded coaxial cables

In order to validate, by means of measurement, some existing equivalent circuit models for the bulk current injection (BCI) test, a procedure is proposed to develop a proper circuit model for the injection clamp and the obtained circuit is introduced into the global one representing the overall cable. A suitable experimental set-up has been built and used. The measured induced voltages at the terminations of shielded coaxial cables are compared with those computed by the equivalent circuit. Upper and lower bounds are quantified in order to assess the order of accuracy of the predicted results.

A hybrid stack-up of printed circuit board for high-speed networking systems

Printed circuit board (PCB) design is getting critical as data rate approaching 25 Gbps (Gigabit per second) and beyond in networking systems. Channel loss, noise coupling and discontinuities are limiting the performance of high-speed channels. Equalization techniques including linear, feed forward and decision feedback are widely used in high-speed SerDes channels to compensate the channel losses. But these are still not sufficient for some extra long channels, and low loss PCB dielectric materials have to be used finally. The consequence is the cost of the networking system soaring significantly. In this paper, a hybrid stack-up is proposed for PCBs used in networking systems. Electrical performance of the hybrid stack-up is investigated in both frequency-domain and time-domain, and a positive conclusion for the hybrid stack-up is reached based on its cost and electrical performances.