Chuen-De Wang

A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method

Based on the conformal mapping technique, a novel macro- π model is proposed to accurately predict the electrical performance of a low pitch-to-diameter ratio (P / D) through-silicon via (TSV) pair on the 3-D IC. The model combines the conventional resistance and inductance (RL) circuit with several parallel capacitances and conductance (CG) circuit. The accuracy-improved CG model rigorously considers the proximity effect. The model can be established by using the derived closed-form formula that is related to geometrical parameters of the TSVs. Compared with the conventional π-type model, the proposed model can significantly reduce the error of CG value from 25% to 2% with respect to a full-wave simulation, and thus the insertion loss can be well predicted from dc to 40 GHz.

Bandwidth Enhancement Based on Optimized Via Location for Multiple Vias EBG Power/Ground Planes

The ground surface perturbation lattice (GSPL) structure is investigated to suppress power noise in the power distribution network of mixed signal circuits. In order to enhance the bandwidth of the noise suppression, the GSPL structure is implemented by using multiple vias in the mushroom-like electromagnetic bandgap structure. Under the concept of multiple vias, the lower and upper bound cutoff frequencies of the bandgap are influenced by the position of the vias. An optimum position for the vias is found to achieve maximum stopband bandwidth. In this paper, the stopband mechanism of GSPL structure is investigated and the corresponding equivalent circuit model is proposed to quickly predict the lower and upper bound cutoff frequencies. Suitable test boards are fabricated and measured to demonstrate the accuracy of the design concept. The result shows that there is a good consistency between simulated, modeled, and measured results.

ABF-Based TSV Arrays With Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments

An Ajinomoto-Build-up-Film (ABF) material is proposed to manufacture through-silicon vias (TSVs) with better signal integrity and lower cost than that of conventional TSVs. The unique advantage of the ABF-based TSVs is that the isolation layer can be thicker than the conventional TSVs, and thus both the insertion loss and crosstalk of the ABF-based TSVs can be improved. An equivalent circuit model is given to predict the electrical behavior of the TSVs and to explain how ratio of the isolation layers thickness to the radius affects the signal integrity. The concept is demonstrated both in frequency- and time-domain simulations. Finally, a test sample of nine-stack ABF-based TSVs is fabricated and assembled. The scanning electron microscope figure supports that the ABF-based TSVs have a thickness-to-radius ratio of 0.667, which is much higher than the conventional TSVs ratio of about 0.1. The measurements also support the simulated results from the equivalent circuit model.

Model and Mechanism of Miniaturized and Stopband-Enhanced Interleaved EBG Structure for Power/Ground Noise Suppression

An interleaved electromagnetic bandgap (EBG) structure is investigated to be with a compact size and wide stopband bandwidth for suppressing power/ground noise in power distribution networks. A design concept of the interleaved EBG structure is given to improve both lower and upper bound cutoff frequencies through varying the pitch of the power and ground vias and validated by measured results. An equivalent circuit model of the 1-D EBG structure is established using transmission-line sections to precisely predict the lower and upper bound cutoff frequencies. Based on the 1-D model, a physical mechanism is found to explain why the interleaved EBG structure can reduce the size and broaden the stopband. As an example, the bandgap of the interleaved EBG structure is in the range from 1.9 to 4.54 GHz. The electrical size, which is normalized to the wavelength in the substrate, and relative bandwidth are 0.071 λgL and 139%, respectively. Unlike other works with tradeoff between size and bandwidth, the interleaved EBG structure can simultaneously achieve substantial improvements on the bandwidth of 51.1% and on the miniaturization of 61.2% compared with the conventional mushroom-like EBG structure.

A Power Bus With Multiple Via Ground Surface Perturbation Lattices for Broadband Noise Isolation: Modeling and Application in RF-SiP

A model and application of the power bus with multiple via ground surface perturbation lattice (MV-GSPL) is investigated in this paper. A 1-D model especially considering the multiple via effects of the MV-GSPL inside the long period coplanar electromagnetic bandgap power planes (LPC-EBG) is proposed. This model can explain the mechanism of the stopband enhancement and accurately predict the effect of multiple via on the stopband behavior. The accuracy of this model is verified both by full-wave simulation and experiments. Based on this model, a MV-GSPL power/ground pair is designed on a radio-frequency (RF) package for system-in-package (SiP) application. A test C-band LNA fabricated by the TSMC 0.18-μ m 1P6M process is packaged on the MV-GSPL substrate for noise immunity test. Both the chip-package co-simulation and experimental results show excellent power noise isolation capability of the RF-SiP package.

Conformal shielding investigation for SiP modules

This paper proposes a complete testing process for conformal shielding techniques. The testing process is systemic and cheap for developing conformal shielding techniques. A 2-D experiment setup and an exact solution are presented to evaluate the properties of metals and metallization techniques. A test vehicle is designed for providing broad band source and low unintended noise. A experiment setup using giga-hertz transverse electromagnetic (GTEM) cell is proposed for providing low noise floor and high sensitivity for measuring small radiation. The test vehicle coated by 0.04 μm sputtering SuS and 1 μm sputtering copper is manufactured and measured to evaluate shielding effectiveness of conformal shielding.

Mold-based compartment shielding to mitigate the intra-system coupled noise on SiP modules

A new technology based on conformal shielding technique called compartment shielding is proposed to isolate the coupled noise between the digital and RF/analog circuits inside system-in-package (SiP) modules. The technology is realized by using a tooth-shaped metal frame to separate different functional circuits. It provides an excellent shielding effectiveness (SE) and reduces the cost, dimensions, and weight compared to the conventional solution. Based on our experience, a test vehicle is designed with a broadband near-field source to evaluate the SE from 0.1 GHz to 10 GHz. The vector network analyzer (VNA) set up with an extremely low noise floor is utilized to measure the insertion loss of the test vehicle. From the measured results, the SE reaches approximately 30 dB before the first resonance appears. The discrepancy between the simulation and measurement are dominated by the fabrication errors and the power leakage at the transitions; however, the isolation over 100 dB with the proposed shield is good enough for many commercial applications, such as hand-held devices and wireless connectivity modules.

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.

Accuracy-improved through-silicon-via model using conformal mapping technique

In this paper, the effects of slow wave and dielectric quasi-TEM modes in through-silicon via (TSV) are analyzed by using the currently used TSV model. By the E-field plot, if pitch-to-diameter ratio is small in TSV structure, it is found out that some electrical behaviour of the TSVs is not well characterized by conventional model. This paper proposes a general and analytic model for the electrical modeling of through-silicon via (TSV) based on the conformal mapping method to modify the conventional model in admittance (CG) parts. With the improved model, the electrical performance of the modified model agrees very well with full-wave simulation up to 40GHz for small normalized pitch TSV.

Parallel-plate noise suppression using a ground surface perturbation lattice (GSPL) structure

The ground surface perturbation lattice (GSPL) structure is proposed to suppress parallel-plate noises by embedding metal crystals into power/ground planes. The design idea is similar to the photonic crystal power/ground layer (PCPL), consisted in high permittivity dielectric material rods embedded between power and ground layer. In contrast to the PCPL structure, the GSPL can be fabricated without employing high cost material and by using standard PCB/package manufacturing process; therefore it is more suitable for real world applications. In this study, it is discussed how the parameters of the GSPL structure influence the bandgap and how to design the GSPL in order to replace PCPL.