Antonio S. Ciccarelli

Front-illuminated full-frame charge-coupled-device image sensor achieves 85% peak quantum efficiency

A high sensitivity front-illuminated charge-coupled device (CCD) technology has been developed by combining the transparent gate technology introduced by Kodak in 1999 with the microlens technology usually employed on interline CCDs. In this new architecture, the microlens is used to focus the incoming light onto the more transparent of the two electrodes. The new sensors offer significant increases in quantum efficiency while maintaining the performance advantages of front-illuminated full-frame CCDs including 3 pA/cm2 typical dark current at 25 degree(s)C, and 55 ke full well in a 6.8 micrometers pixel.

A modular, high performance, 2 /spl mu/m CCD-BiCMOS process technology for application specific image sensors and image sensor systems on a chip

A 2 /spl mu/m BiCMOS process module has been developed for incorporation into existing charge-coupled device (CCD) image sensor processes. The modular process architecture allows integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics, and enables on-chip integration of desired analog and digital circuit functions with the image sensor. To our knowledge this is the first demonstration of high performance CCD, 2 /spl mu/m CMOS, and an isolated vertical NPN integrated on the same chip.<<ETX>>

Very high resolution 8,002-pixel trilinear color image sensor

A very high resolution 8,002-pixel trilinear image sensor is under development to meet customer requirement as they progress toward the next generation graphic arts scanning and industrial inspection systems. High-performance features will include an enhanced color filter scheme providing improved blue and green responsivity; better filter uniformity; lower dark current; improved, uncooled dynamic range to 15 bits; and will provide over 400,000 electrons of charge capacity. This sensor maintains a common optical length to Kodaks current line of long trilinear imagers.

Ultrahigh-resolution 14,400-pixel trilinear color image sensor

An ultra-high resolution 14,400 pixel trilinear image sensor is under development to meet customer requirements as they progress into next generation, high-end color scanning systems. High-performance features being incorporated into this device include an enhanced color filter scheme providing improved blue and green responsivity, electronic exposure control, and antiblooming protection. To our knowledge, this will be the highest resolution trilinear sensor to date and is being designed to provide common optical length to Kodaks current line of long trilinear imagers.

Modular high-performance 2-μm CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.