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Dive into the research topics where Herbert J. Erhardt is active.

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Featured researches published by Herbert J. Erhardt.


international conference on asic | 1994

A modular, high performance, 2 /spl mu/m CCD-BiCMOS process technology for application specific image sensors and image sensor systems on a chip

R.M. Guidash; Paul P. Lee; J.M. Andrus; Antonio S. Ciccarelli; Herbert J. Erhardt; John Fischer; Eric J. Meisenzahl; Robert H. Philbrick; Goodwin Ting

A 2 /spl mu/m BiCMOS process module has been developed for incorporation into existing charge-coupled device (CCD) image sensor processes. The modular process architecture allows integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics, and enables on-chip integration of desired analog and digital circuit functions with the image sensor. To our knowledge this is the first demonstration of high performance CCD, 2 /spl mu/m CMOS, and an isolated vertical NPN integrated on the same chip.<<ETX>>


IS&T/SPIE's Symposium on Electronic Imaging: Science & Technology | 1995

Modular high-performance 2-μm CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

R. Michael Guidash; Paul P. Lee; J. M. Andrus; Antonio S. Ciccarelli; Herbert J. Erhardt; John Fischer; Eric J. Meisenzahl; Robert H. Philbrick; Timothy J. Kenney

A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.


Archive | 1992

COLOR IMAGE SENSOR HAVING AN OPTIMUM EXPOSURE TIME FOR EACH COLOR

Herbert J. Erhardt


Archive | 1989

Charge-coupled device (CCD) imager and method of operation

Herbert J. Erhardt


Archive | 1990

Transfer gate for photodiode to CCD image sensor

Herbert J. Erhardt; Edward T. Nelson; Eric G. Stevens


Archive | 2010

Automotive imaging system for recording exception events

Herbert J. Erhardt; Robert M. Guidash


Archive | 1995

Solid state image sensor with selectable resolution

Antonio S. Ciccarelli; Herbert J. Erhardt; Martin Potucek


Archive | 1990

Charge-coupled device having improved transfer efficiency

Herbert J. Erhardt


Archive | 1990

Charge-coupled imager with dual gate anti-blooming structure

Teh-Hsuang Lee; Herbert J. Erhardt


Archive | 1992

Transfer region design for charge-coupled device image sensor

Constantine N. Anagnostopoulos; Herbert J. Erhardt; Eric G. Stevens; Robert H. Philbrick

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