Paul P. Lee

A modular, high performance, 2 /spl mu/m CCD-BiCMOS process technology for application specific image sensors and image sensor systems on a chip

A 2 /spl mu/m BiCMOS process module has been developed for incorporation into existing charge-coupled device (CCD) image sensor processes. The modular process architecture allows integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics, and enables on-chip integration of desired analog and digital circuit functions with the image sensor. To our knowledge this is the first demonstration of high performance CCD, 2 /spl mu/m CMOS, and an isolated vertical NPN integrated on the same chip.<<ETX>>

A low-cost, smart-power BiCMOS driver chip for medium power applications

A smart-power integrated circuit has been developed intended for low-cost, medium power switching, and drive applications. The die incorporates CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies. Modeling and optimization of process and circuit parameters resulted in a 7.66 mm/sup 2/ chip with four independently controlled outputs each capable of switching up to 1 ampere at 30 volts, at a frequency of up to 2 MHz.<<ETX>>

Modular high-performance 2-μm CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.