Anup Sarkar

Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

Abstract A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poissons equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.

Performance Analysis of a Front High-K Gate Stack Dual-Material Tri-gate SON MOSFET

This present work encompasses the analytical modeling of a front high-K gate stack dual-material tri-gate SON MOSFET. By solving the three-dimensional Poisson’s equation, the expression for surface potential of the proposed device is obtained. In addition, the electric field of the device is also calculated. The results obtained are compared with the model’s single-metal counterpart. The extent of agreement between the analytical results and simulated results obtained from a 3-D device simulator, namely Atlas, Silvaco, is quite good that validates our proposed model.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

Induction Heating of an Aluminum Billet: A Numerical Study of the Thermal Behavior

In the present work, the heat transfer behavior during induction heating of a cylindrical aluminum billet is performed numerically. The heating process is represented by the energy conservation equation where the heat generation during heating is added as a volumetric source term. The evolution of latent heat during melting is also added as a volumetric source term. The continuity and the momentum conservation equations are considered to represent the flow field after melting starts. These governing equations are solved based on the control volume method. The enthalpy update scheme is used for evolution of melt-fraction during heating. The work predicts the evolution of temperature during heating, the distributions of temperature and melt-fraction in the domain. Subsequently, a parametric study is also performed.