Anindya Jana

Design and simulation of hybrid CMOS–SET circuits

Abstract Single electron devices have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A new methodology to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETs) and CMOS interfaces. In this work a room temperature operable hybrid CMOS–SET inverter circuit, hybrid CMOS–SET NOR gate and their Voltage Transfer Characteristics (VTCs) are proposed. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. Based on the hybrid CMOS–SET inverter, other logic gates such as NAND, NOR, AND, OR, XOR and XNOR are proposed. All the circuits are verified by means of T-Spice simulation software.

Design and performance analysis of reversible logic based ALU using hybrid single electron transistor

The Co-integration of SET (Single Electron Transistor) and CMOS is the new evolution for the stunning growth in modern semiconductor industry. In the present work we have demonstrated that the successful implementation of ALU (Arithmetic Logic Unit) using hybrid SET-CMOS and hybrid SET-CMOS based Reversible logic gates. We have represented the simulation output of the both cases and a comparison has made between different design methods. The experimental delay measurement has also been presented. All the simulations are done using Hybrid SET-CMOS technology with the help of MIB and BSIM4.6.1 model in tanner environment to realize the better performance.

Hybrid Single Electron Transistor-Based Low Power Consuming BCD Adder Circuit in 65 Nanometer Technology

Traditional method of device designing is getting replaced by emerging trend of hybrid SET-CMOS logic. Mutual integration between the two has led towards ultra-dense circuitry as well as ultra low power consuming devices. Here a BCD adder circuit is realized with the help of hybrid single-electron transistor technology in 65 nm node. Power analysis and power-delay product for that adder circuit are also presented both numerically and graphically in comparison to the conventional CMOS logic, respectively.

Hybrid single electron transistor based octal to binary encoder in 22 nanometer technology

The co fabrication of SET & CMOS technology has already proved its ability to bring a drastic change in the era of nanodimensional devices. In our present work a well known combinational circuit, octal to binary encoder is demonstrated using hybrid SET-CMOS technology in 22 nanometer node. We have presented power analysis for the circuit here. Power delay product for the circuit has also been done and a comparison is made with the conventional CMOS based circuit. Simulations are done using TCAD with the help of MIB model and BSIM4.6.1 model to establish the feasibility of the proposed model in case of room temperature operation.

Hybrid Single Electron Transistor Based Low Power Consuming Odd Parity Generator and Parity Checker Circuit in 22 nm Technology

Co-fabrication between single electron transistor (SET) and CMOS technology has already proved to be feasible in production of future low power ultra dense circuitry. Mutual integration between this two can thus be efficient in computing applications. Here, an odd parity generator and parity checker circuit is build up with hybridization of SET-CMOS technology using Mahapatra-Ionescu-Banerjee (MIB model) and BSIM 4.6.1 model. Power consumption and PDP are also calculated and compared numerically and graphically with the conventional CMOS technology.