Arch Zaliznyak

Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

The SoPC (system on a programmable chip) aspects of the Stratix GX/spl trade/ FPGA with 3.125 Gbps SERDES are described. The FPGA was fabricated on a 0.13 /spl mu/m, 9-layer metal process. The 16 high-speed serial transceiver channels with clock data recovery (CDR) provides 622-Megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described is the implementation of 39 source-synchronous channels at 100 Mbps to 1 Gbps, utilizing dynamic phase alignment (DPA). The implementation and integration of the FPGA logic array (with its own hard IP) with the CDR and DPA channels involved grappling with SoC design issues and methodologies.

Multi-protocol embedded PCS IP in a FPGA-SOC

Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be bounded intelligently. Major architectural enhancements were necessary instead of a simple performance upgrade of the previous Hard IP. Verification complexity mandated design and verification re-use. Emulation and vendor soft IF interoperability testing was another strategy employed for first silicon success