Rakesh H. Patel

Interconnect enhancements for a high-speed PLD architecture

As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.

A 3.3-V programmable logic device that addresses low power supply and interface trends

This paper discusses a 3.3 V programmable logic device family which provides up to 130 Kgates. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 6,656 logic elements and circuit techniques to address low power supply and interface trends. It is designed on a 0.35 /spl mu/m triple metal-dual oxide process to operate in a 3.3 V only, 5 V only or 3.3 V-5 V systems. Under worst case operating conditions it was observed to have a typical system operating frequency of 90 MHz. The EPF10K50V is the first member of the second-generation FLEX 10K family.

Power estimation and thermal budgeting methodology for FPGAs

The method used for power estimation and thermal budgeting on an FPGA product line, fabricated using 90 nm technology, is described in this paper. It addresses the reasons why state-of-the-art processes create power concerns on FPGAs, and describes methodologies that provide more relevant power and junction temperature estimations. Finally it suggests what can be done to improve the power budget and to balance the trade-offs between power and performance.

A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability

This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 560 product term based macrocells and circuit techniques to achieve an overall 90.7 MHz system operating frequency. The device is designed to operate in a 3.3 V or 5 V systems. It has built-in JTAG boundary scan for improving testability and in-system programmability for ease of manufacturing.

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops

This paper examines two popular bang-bang CDR architectures: one is with a conventional RC loop filter which often involves a 3rd order loop design and the other is with a separate proportional path which involves a straightforward 2nd order loop design. Design considerations for the two architectures are compared as a function of various design parameters that impact jitter tolerance. Theoretical findings are confirmed by experimental results of a wide-range bang-bang CDR fabricated in 90nm CMOS

A signal integrity-based link performance simulation platform

This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization. This platform was created using MATLAB, qualified against Agilents ADS SI suite, and correlated with measurements. This paper also describes the practical uses of such a simulator developed at Altera to predict link performance over backplanes.

Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

The SoPC (system on a programmable chip) aspects of the Stratix GX/spl trade/ FPGA with 3.125 Gbps SERDES are described. The FPGA was fabricated on a 0.13 /spl mu/m, 9-layer metal process. The 16 high-speed serial transceiver channels with clock data recovery (CDR) provides 622-Megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described is the implementation of 39 source-synchronous channels at 100 Mbps to 1 Gbps, utilizing dynamic phase alignment (DPA). The implementation and integration of the FPGA logic array (with its own hard IP) with the CDR and DPA channels involved grappling with SoC design issues and methodologies.

PELE: Pre-emphasis a Equalization Link Estimator to Address the Effects of Signal Integrity Limitations

This paper discusses a methodology employed to create a tool that quantifies the effects of signal integrity limitations particularly for high-speed applications. The tool is based on a platform of routines which predict performance over high-speed links. It contains routines that optimize transmitter pre-emphasis and receiver equalization that lead to superior BER performance. The tool is qualified against Agilents ADS simulator and correlated to measurements

Multi-protocol embedded PCS IP in a FPGA-SOC

Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be bounded intelligently. Major architectural enhancements were necessary instead of a simple performance upgrade of the previous Hard IP. Verification complexity mandated design and verification re-use. Emulation and vendor soft IF interoperability testing was another strategy employed for first silicon success

Nonlinear behavior study in digital bang-bang PLL

A simple high-performance nonlinear digital PLL is fabricated in 90 nm CMOS with operating range of 0.5 to 3.25 GHz and 1.24 ps jitter. New insights into the PLL behavior are discussed. The classical “20Log” in-band phase noise tracking does not hold for the type of nonlinear digital loops.