Arda Simsek

Towards chip-scale optical frequency synthesis based on optical heterodyne phase-locked loop

An integrated heterodyne optical phase-locked loop was designed and demonstrated with an indium phosphide based photonic integrated circuit and commercial off-the-shelf electronic components. As an input reference, a stable microresonator-based optical frequency comb with a 50-dB span of 25 nm (~3 THz) around 1550 nm, having a spacing of ~26 GHz, was used. A widely-tunable on-chip sampled-grating distributed-Bragg-reflector laser is offset locked across multiple comb lines. An arbitrary frequency synthesis between the comb lines is demonstrated by tuning the RF offset source, and better than 100Hz tuning resolution with ± 5 Hz accuracy is obtained. Frequency switching of the on-chip laser to a point more than two dozen comb lines away (~5.6 nm) and simultaneous locking to the corresponding nearest comb line is also achieved in a time ~200 ns. A low residual phase noise of the optical phase-locking system is successfully achieved, as experimentally verified by the value of -80 dBc/Hz at an offset of as low as 200 Hz.

Optical synthesis using Kerr frequency combs

An InP-based photonic integrated circuit was demonstrated for offset locking an on-chip broadly tunable laser to a heterogeneously integrated optical frequency comb oscillator based on a crystalline whispering gallery mode resonator. Optical tuning within 60nm band is demonstrated. The locked laser has excellent spectral purity, sub-kHz linewidth, and good frequency stability.

Heterodyne locking of a fully integrated optical phase-locked loop with on-chip modulators

We design and experimentally demonstrate a highly integrated heterodyne optical phase-locked loop (OPLL) consisting of an InP-based coherent photonic receiver, high-speed feedback electronics, and an RF synthesizer. Such coherent photonic integrated circuits contain two widely tunable lasers, semiconductor optical amplifiers, phase modulators, and a pair of balanced photodetectors. Offset phase-locking of the two lasers is achieved by applying an RF signal to an on-chip optical phase modulator following one of the lasers and locking the other one to a resulting optical sideband. Offset locking frequency range >16  GHz is achieved for such a highly sensitive OPLL system which can employ up to the third-order-harmonic optical sidebands for locking. Furthermore, the rms phase error between the two lasers is measured to be 8°.

An Ultra-Low-Power Dual-Polarization Transceiver Front-End for 94-GHz Phased Arrays in 130-nm InP HBT

We present a fully integrated 94-GHz transceiver front-end in a 130-nm/1.1-THz

Ultra-Low-Power Components for a 94 GHz Transceiver

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Power-Efficient Kerr Frequency Comb Based Tunable Optical Source

InP HBT process. Low power is obtained through low-voltage design and high transistor gain. The IC is designed for multi-function, dual-polarization phased arrays. At 1.5-V collector bias, in dual-polarization simultaneous receiving mode, the IC has 21-dB gain, <9.3-dB noise figure, and consumes 39 mW, while in transmitting mode with time-duplexed vertical and horizontal outputs, the transceiver front-end achieves 5-dBm output power, 22-dB gain, and consumes 40 mW. At 1-V collector bias, in dual-polarization simultaneous receiving mode, the IC has 22.7-dB gain, <8.9-dB noise figure, and consumes 26 mW, while in transmitting mode, it has 22-dB gain and the saturated output power of 1.4 dBm with 29-mW power consumption.

Evolution of Chip-Scale Heterodyne Optical Phase-Locked Loops Toward Watt Level Power Consumption

We present a fully-integrated 94 GHz transceiver front-end in a 130 nm / 1.1 THz fmax InP HBT process. Low power is obtained through low-voltage design and high transistor gain. The IC is designed for multi-function, dual-polarization phased arrays. At 1.5 V collector bias, in dual-polarization simultaneous receiving mode, the IC has 21 dB gain, <; 9.3 dB noise figure, and consumes 39 mW, while in transmitting mode with time-duplexed vertical and horizontal outputs, the transceiver achieves 5 dBm output power, 22 dB gain, and consumes 40 mW. At 1.0 V bias, in dual-polarization simultaneous receiving mode, the IC has 22.7 dB gain, <; 8.9 dB noise figure, and consumes 26 mW.