Arifur Rahman

An Ion-Sensitive Floating Gate FET Model: Operating Principles and Electrofluidic Gating

We present a model that can be used to compute the charging and potential at any point of the electrochemical system comprising the ion-sensitive floating gate FET (ISFGFET) exposed to an electrolyte solution. In contrast to ion-sensitive FETs, the sensor has an additional control input gate. The model predicts the possibility for electrofluidic gating when the control gate (CG) is used in conjunction with a reference electrode (RE). Electrofluidic gating is the field-effect control over the electric double layer. We consider the applicability of electrofluidic gating in realizable devices and simulate the relationships between oxide properties and electrolyte solution to varying potentials of the CG and the RE. The oxide/electrolyte solution model is merged to the SPICE model of the transistor to create a unified model that can be used to simulate the transfer characteristics of the sensor in absolute terms to change input and electrolyte solution conditions. We simulate the sensor transfer characteristics with common Al2O3 surface to change the pH of the electrolyte solution and compare them to measurements. The results clarify the operation of ISFGFET and its applicability in electrofluidic gating.

Surface Functionalization of Ion-Sensitive Floating-Gate Field-Effect Transistors With Organic Electronics

Electrically conducting polymers are advantageous hybrid materials for microelectronic biosensors due to their high bandgap sensitivity, possibilities for nanoscale surface area formation, and well-developed surface bioconjugation strategies. In this paper, we investigated whether those organic conductors can also be used to functionalize ion-sensitive floating-gate field-effect transistors (ISFGFETs) designed to measure biological binding events. We first subjected our device to 100% relative humidity (RH) and proved its viability in such a humid environment. Subsequently, we drop-casted viscoelastic polyaniline emeraldine salt on pristine transistors to construct organo-functionalized devices. The modified ISFGFETs were stable in aqueous environments and sensitive to cationic polyethyleneimine. The directions of the ISFGFET threshold voltage (VT) shifts agree with the corresponding open-circuit potential variations for the same reaction and pH-sensitive behaviors of Al2O3 sensing layer on the transistor. Such organo-modified ISFGFET sensor arrays are promising alternatives to traditional conductive polymer-based potentiometric biosensors due to their signal amplification, high throughput, and scalability advantages.

Embedded cooling technologies for densely integrated electronic systems

In modern integrated systems, interconnect and thermal management technologies have become two major limitations to system performance. In this paper, a number of technologies are presented to address these challenges. First, low-loss polymer-embedded vias are demonstrated in thick wafers compatible with microfluidics. Next, fluidic I/Os for delivery of fluid to microfluidic heat sinks are demonstrated in assembled 2.5D and 3D stacks. Then thermal coupling between dice in 2.5D and 3D systems is explored. Lastly, the utility of microfluidic cooling is demonstrated through an FPGA, built in a 28nm process, with a monolithically integrated microfluidic heat sink.

Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)

This paper presents an overview of design and manufacturing readiness for silicon interposer based 3D integration. We present a field programmable gate array research and development vehicle to demonstrate the capabilities of 3D technology. The characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on silicon interposer. We also provide an overview of various process steps involved in the creation and integration of TSV on silicon interposer and methods to optimize them for performance and cost. Cost reduction can be achieved by process optimization at an integrated or holistic level, better alignment of interposer specification with application requirements, and die-package co-design.

Arria™ 10 device architecture

This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.

Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

Microfluidic cooling has been demonstrated as an effective means of cooling microelectronic circuits with a very low convective thermal resistance and potential for integration in close proximity to the area of heat generation. However, microfluidic cooling experiments to date have been limited to silicon with resistive heaters representing the heat generating circuitry. In this paper, a micropin-fin heat sink is etched into the back side of an Altera Stratix V field-programmable gate array (FPGA), built in a 28-nm CMOS process. Thermal and electrical measurements are made running a benchmark pulse compression algorithm on the FPGA. Deionized water is used as a coolant with flow rates ranging from 0.15 to 3.0 mL/s and inlet temperature ranging from 21 °C to 50 °C. An average junction-to-inlet thermal resistance of 0.07 °C/W is achieved.

Energy-efficient architecture and enabling technology for advanced SOCs

This session highlights energy-efficient architectures, implementations of application-specific SoC in advanced process technologies, and silicon photonics building blocks for chip-scale optical interconnects.