Jeffrey Tyhach
Altera
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Publication
Featured researches published by Jeffrey Tyhach.
IEEE Journal of Solid-state Circuits | 2005
Jeffrey Tyhach; Bonnie I. Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan
As FPGAs integrate into high-speed systems, performance and signal integrity become more important in I/O design. This paper describes the development of an FPGA design to support 1.6 Gb/s differential source-synchronous standards and 300 MHz external memory interfaces. Speed and performance were achieved using circuits such as differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. Programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3-V voltage tolerance are features of the I/O buffer. In addition, DLLs and programmable phase-offset circuits were used to obtain precise timing control. The chip was manufactured on a 90-nm CMOS process.
custom integrated circuits conference | 2004
Jeffrey Tyhach; Bonnie I. Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan
As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6 Gbps differential source-synchronous standards and 300 MHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90 nm CMOS process.
custom integrated circuits conference | 2015
Jeffrey Tyhach; Michael D. Hutton; Sean R. Atsatt; Arifur Rahman; Brad Vest; David Lewis; Martin Langhammer; Sergey Shumarayev; Tim Tri Hoang; Allen Chan; Dong-myung Choi; Dan Oh; Hae-Chang Lee; Jack Chui; Ket Chiew Sia; Edwin Yew Fatt Kok; Wei-Yee Koay; Boon-Jin Ang
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.
Archive | 2005
Tzung-Chin Chang; Xiaobao Wang; Henry Kim; Chiakang Sung; Khai Nguyen; Bonnie I. Wang; Jeffrey Tyhach; Gopinath Rangan
Archive | 2006
Jeffrey Tyhach; Chiakang Sung; Khai Nguyen; Sanjay K. Charagulla; Ali Burney
Archive | 2003
Jeffrey Tyhach; Bonnie I. Wang; Chiakang Sung; Khai Nguyen
Archive | 2004
Cheng-Hsiung Huang; Chih-Ching Shih; Jeffrey Tyhach; Guu Lin; Chiakang Sung; Stephanie Tran
Archive | 2005
Jeffrey Tyhach; Bonnie I. Wang; Yan Chong; Chiakang Sung
Archive | 2012
Karthik Chandrasekar; Arifur Rahman; Jeffrey Tyhach
Archive | 2015
Christopher F. Lane; Giles Powell; Jeffrey Tyhach