Muhannad S. Bakir

A 3D-IC Technology with Integrated Microchannel Cooling

A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal resistance of 0.24°C/W. The demonstrated silicon die contain a through-silicon copper via density of 2500/cm2 integrated within the microchannel heat sink.

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation

This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical interconnects are used to enable optical signal routing to all levels of the 3D stack, and the microfluidic interconnects are used to cool each level in the 3D stack and thus enable stacking of high-performance (high-power) dice. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Power dissipation in microprocessors will reach a level that necessitates chip-level liquid cooling in the near future. An on-chip microfluidic heat sink can reduce the thermal interfaces between an IC chip and the convective cooling medium. Through wafer-level processing, integrated thermal-fluidic I/O interconnects enable on-chip microfluidic heat sinks with ultrasmall form factor at low-cost. This letter describes wafer-level integration of microchannels at the wafer back-side with through-wafer fluidic paths and thermal-fluidic input/output interconnection for future generation gigascale integrated chips.

3D stacking of chips with electrical and microfluidic I/O interconnects

Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100 W/cm2 and require more than 100 A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [Bakir, et. al., (2007)]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the dies low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.

Wafer-level microfluidic cooling interconnects for GSI

We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 /spl mu/m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer to form enclosed microchannels. Through chip holes and polymer pipes are used as the inlet/outlet interconnects. Different channel array designs were described and the pressure drop was estimated for a heat flux of 100 W/cm/sup 2/ with DI water flow rate. The resulting cooling scheme offers a simple and compact solution to transfer cooling liquid directly into a GSI chip and is fully compatible with flip-chip packaging.

Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections

An electrical-optical chip input-output (I/O) interconnection technology called sea of polymer pillars (SoPP) is presented. SoPP provides highly process-integrated and mechanically flexible (compliant) electrical-optical die-to-board interconnections that mitigate thermo-mechanical expansion mismatches. The I/O density of SoPP exceeds 10/sup 5//cm/sup 2/. The compliance of the polymer pillars is shown to be 3-5 /spl mu/m/mN. Approximately 50% input optical coupling efficiency into a volume grating coupler through a set of polymer pillars is demonstrated.

Interconnecting device opportunities for gigascale integration (GSI)

In recent years interconnecting devices have become primary limits on the performance, energy dissipation, signal integrity, and productivity of gigascale integration (GSI). Opportunities to address the interconnect problem include new materials and processes, reverse scaling, novel microarchitectures, three-dimensional integration, input/output interconnect enhancements, RF wireless interconnects and microphotonics.