Arindam Sanyal

A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique

This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.

An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs

This brief presents a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters that achieves a 95% reduction in switching energy over the conventional SAR. The switching energy has been calculated by taking into account both the power drawn from reference and the power consumed by the switches themselves. The frequency dependence of the switching energy has been studied and the proposed technique presents ways to maintain high energy efficiency over the entire frequency range of operation. The results have been verified through behavioral and SPICE simulations.

Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization

This brief presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined analog-to-digital converters (ADCs). It does not modify the original analog signal path except for the addition of a comparator decision time binary quantizer built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth. Simulation results for a 12-bit pipelined ADC show that the proposed technique can improve the signal- to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) from 44 and 48 dB to 72 and 86 dB, respectively. The SNDR convergence time is less than 3 × 106 cycles.

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.

A single SAR ADC converting multi-channel sparse signals

This paper presents a simple but high performance architecture for multi-channel analog-to-digital conversion. Based on compressive sensing, only one SAR ADC is needed to convert multi-channel sparse inputs, leading to significant analog power saving and hardware saving. Moreover, it helps avoid problems occurring in conventional multi-channel ADCs such as timing skew, offset mismatch, and gain mismatch. A 12-bit SAR ADC converting 4-channel sparse signals simultaneously is designed in 130nm CMOS process. The design reaches a SNDR of 66.3dB and consumes an average power of 58μW at the sampling frequency of 1MHz. The L1 minimization method is chosen to reconstruct the input signals. The single-tone and multi-tone inputs can be reconstructed with a minimum precision of 68dB and 55dB THD, respectively.

Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit

This paper presents a novel dynamic element matching (DEM) technique for multi-bit ΔΣ digital-to-analog converters (DACs). The proposed technique can address errors due to both static element mismatch and dynamic inter-symbol-interference (ISI). The proposed technique ensures no ISI-induced distortion even at large signal amplitudes by de-correlating the instantaneous number of DAC transitions from the signal. It can shape the total number of transitions and whiten the individual transition sequence, thereby significantly reducing the in-band ISI errors. The proposed technique can be easily extended to higher-order shaping for both static mismatch and ISI errors. An efficient hardware implementation based on the vector-quantizer mismatch shaping framework is also presented. Simulation results show that the proposed technique can significantly improve DAC linearity in presence of both static mismatch and dynamic ISI errors.

\Delta\Sigma

This brief presents a novel mismatch shaping technique for multibit delta-sigma digital-to-analog converters (DACs). It uses the intrinsic quantization noise to randomize the element selection. Different from most existing mismatch shaping techniques that increase the element transition activity, the proposed technique keeps the same transition rate as that for the basic thermometer coding scheme. As a result, it produces much lower intersymbol interference (ISI)-induced distortions. Moreover, it does not produce tones and can high-pass shape the mismatch errors, unlike thermometer coding that produces large distortions due to static mismatch. An efficient hardware implementation based on the vector-quantizer mismatch shaping framework is also presented. Simulations show that the proposed technique can significantly improve DAC linearity in the presence of both ISI and mismatch errors.

Modulators

This brief presents a fast-converging hybrid successive approximation register (SAR) analog-to-digital converter (ADC) based on the radix-3 and radix-2 search approaches. The radix-3 approach achieves 1.6 bits/cycle, and the radix-2 approach mitigates the effect of comparator offset and improves the accuracy of the ADC. Incorporating clock gating of comparators and efficient switching of capacitors, the proposed hybrid ADC demonstrates promising balance between hardware complexity and speed and can achieve equivalent signal-to-noise-and-distortion-ratio (SNDR) with less capacitors compared with radix-3 SAR ADC. Behavioral simulation-based results verify operation and merit of the proposed architecture. An 11-bit 45-MS/s prototype with 5% capacitor mismatch in 180-nm CMOS was simulated in SPICE and achieves 67 dB of SNDR after calibration.

A thermometer-like mismatch shaping technique with minimum element transition activity for multibit ΔΣ DACs

This paper presents techniques to address static and dynamic errors in high performance continuous-time (CT), ΔΣ modulators. The inter-symbol interference (ISI) model is presented and existing ISI reduction techniques are reviewed. A novel technique has been presented which can high-pass shape both static mismatch and ISI error of each element of a multi-bit DAC while decorrelating the instantaneous number of transitions from the input signal. The proposed technique can easily be extended to higher order shaping for both static mismatch and ISI errors. Simulation results show that the proposed technique can improve DAC linearity significantly in presence of both static mismatch and ISI error.

A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relatively low resolution digital-to-analog converter (DAC). The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least significant bit (LSB) comparisons. Three estimation schemes are studied and the optimal Bayes estimator is chosen for a prototype 11-b ADC in 65-nm CMOS. The measured SNR is improved by 7 dB with the proposed noise reduction technique. Overall, it achieves 10.5-b effective number of bits while operating at 100 kS/s and consuming