Xiyuan Tang

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.

A 0.7-V 0.6-

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relatively low resolution digital-to-analog converter (DAC). The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least significant bit (LSB) comparisons. Three estimation schemes are studied and the optimal Bayes estimator is chosen for a prototype 11-b ADC in 65-nm CMOS. The measured SNR is improved by 7 dB with the proposed noise reduction technique. Overall, it achieves 10.5-b effective number of bits while operating at 100 kS/s and consuming

\mu \text{W}

0.6~\mu \text{W}

100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

from a 0.7-V power supply.

Comparator common-mode variation effects analysis and its application in SAR ADCs

The effects of comparator input common-mode voltage Vcm are analyzed in this paper. The analysis clearly shows a trade-off in the choice of Vcm in terms of offset, noise, power and speed. Based on the analysis, an energy efficient SAR ADC switching technique is proposed with less Vcm variation and better linearity compared with the widely used monotonic switching technique. Both the simulation results and prototype measured results match with the analysis.

A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration

This paper presents a time-interleaved (TI) SAR analog-to-digital converter (ADC) with a fast variance-based timing-skew calibration technique. It uses a single-comparator-based window detector (WD) to calibrate the timing skew. The WD can suppress variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The proposed technique brings collateral benefit of offset mismatch calibration. After timing-skew calibration, a prototype 10-b 800-MS/s ADC in 40-nm CMOS achieves the Nyquist-rate SNDR of 48 dB and consumes 4.9 mW, leading to the Walden FoM of 29.8-fJ/conversion step.

A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS

This paper presents a 10-bit high-speed two-stage SAR ADC. Each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. By doing this, the SAR logic delay and power are significantly reduced. A modified bidirectional single-side switching technique is used to optimize the comparator speed and offset by controlling the input common mode voltage Vcm. To suppress the comparator offset mismatch induced nonlinearity, redundancy and a shared pre-amplifier are employed in the second fine stage. The pre-amplifier is implemented using a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55dB peak SNDR at 200MS/s sampling rate without any calibration. It consumes 750μW from 1.1V power supply, leading to a Walden FOM of 8.6fJ/conversion-step.

A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration

This paper presents a time-interleaved (TI) successive-approximation-register (SAR) ADC with a fast variance-based timing-skew calibration technique. It uses a single comparator-based window detector to calibrate the timing skew. It has low-hardware cost and 104 times faster convergence speed compared to prior variance-based timing skew calibration technique. The proposed technique brings collateral benefits of offset mismatch calibration. A prototype 10-b 800MS/s ADC in 40nm CMOS achieves Nyquist-rate SNDR of 48 dB and consumes 9.8mW, leading to a Walden FoM of 59-fJ/conversion-step.

A 0.04-mm 2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration

This paper presents a low-power and small-area VCO-based closed-loop ΔΣ ADC with two highlights. First, the ADC has a distributed modular architecture. It consists of repetitive slices, which simplifies both schematic and layout design. It allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked averaging (CLA) capability of dual VCO-based integrator. It ensures high linearity in the presence of large DAC mismatches. A prototype ADC in 130nm CMOS occupies only 0.04mm2. It achieves 71dB SNDR over 1.7MHz BW while sampling at 250MS/s and consuming 0.9mW under a 1.2V supply.